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US 4,794,561 AGranted
Static ram cell with trench pull-down transistors and buried-layer ground plate
AssigneeIntegrated Device Technology, Inc.
InventorFu-Chieh Hsu
Life of this patent
Estimating the term…
Abstract
Disclosed is a (4T-2R) SRAM cell and method which achieves a much reduced cell area through the combined use of vertical trench pull-down n-channel transistors and a buried-layer ground plate. The reduced cell area allows the fabrication of a higher density SRAM for a given set of lithographic rules. The cell structure also allows the implementation of a (6T) SRAM cell with non-self-aligned polysilicon p-channel pull-up transistors without appreciably enlarging the cell area.
Claims4
A SRAM cell comprising in combination:
- a silicon chip including
- a first bit line;
- a word line;
- a second bit line;
- a power supply line;
- a buried layer ground plate;
- a first resistor;
- a second resistor;
- a first transistor configured as a transfer transistor, said first transistor having source means connected to said first input line, a gate connected to said word line, and drain means coupled by said first resistor to said power supply line;
- a second transistor configured as a pull-down transistor, said second transistor having source means connected to said buried layer ground plate, a gate coupled by said second resistor to said power supply line, and drain means connected to said first transistor drain means;
- a third transistor configured as a pull-down transistor, said third transistor having source means connected to said buried layer ground plate, a gate connected to said first transistor drain means, and drain means connected to said second transistor gate at least one of said second and said third transistors being produced in a trench with said one of said transistors source means extending into said buried layer ground plate;
- and
- a fourth transistor configured as a transfer transistor, said fourth transistor having source means connected to said second transistor gate, a gate connected to said word line, and drain means connected to said second bit line.
10 more elements
A SRAM cell comprising in combination:
- a silicon chip including
- a first bit line;
- a word line;
- a second bit line;
- a power supply line;
- a buried layer ground plate;
- a first transistor configured as a transfer transistor, said first transistor having source means connected to said first input line, a gate connected to said word line, and drain means;
- a second transistor configured as a pull-down transistor, said second transistor having source means connected to said buried layer ground plate, a gate, and drain means connected to said first transistor drain means;
- a third transistor configured as a pull-down transistor, said third transistor having source means connected to said buried layer ground plate, a gate connected to said first transistor drain means, and drain means connected to said second transistor gate, at least one of said second and said third transistors being produced in a trench with said one of said transistors source means extending into said buried layer ground plate;
- a fourth transistor configured as a transfer transistor, said fourth transistor having source means connected to said second transistor gate, a gate connected to said word line, and drain means connected to said second bit line;
- a fifth transistor having source means connected to said first transistor drain means, a gate connected to said second transistor gate, and drain means connected to said power supply line;
- and
- a sixth transistor having source means connected to said second transistor gate, a gate connected to said first transistor drain means, and drain means connected to said power supply line.
10 more elements
Dependencies are inferred from the claim text.