Floating-point normalizing circuit

A floating-point arithmetic circuit adapted to receive at least two multi-bit numbers, which includes a normalizing circuit receiving the two multi-bit numbers to generate a shift amount signal, a pair of shifters receiving the two multi-bit numbers, respectively, to shift the respective input numbers in accordance with the shift amount signal, a processing unit receiving the outputs of the pair of shifters to carry out a predetermined arithmetic operation between the inputted numbers and to output the result of operation in the form of a mantissa, and an encoder receiving the shift amount signal to generate an exponent part for the above mentioned arithmetic operation, wherein the improvement is that the normalizing circuit comprises a plurality of unitary circuits each including a pair of binary inputs, a unitary shift signal output, a carry input, and a carry output internally connected through a controlled gate means to the carry input, the unitary circuits being adapted to receive at their binary inputs different digit position bits of each of the two input numbers, respectively, but each of the unitary circuits receiving at its one pair of binary inputs the same digit position bits of the two input numbers, the carry input of each unitary circuit being connected to the carry output of an adjacent more significant digit unitary circuit so that a carry signal is transferred from the most significant digit unitary circuit to the least significant digit unitary circuit, each of the unitary circuit functioning to turn off the controlled gate means and to generate a unitary shift signal when a predetermined logic level is detected in at least one input of the binary inputs and a predetermined carry signal is received at its carry input, whereby the position of the circuit generating the unitary shift signal is indicative of the amount of required shift for normalization.