Cache memory architecture for microcomputer speed-up board

A method for enhancing the speed of operation of a computer having a plurality of devices including a first microprocessor coupled to a main memory via an address bus, said computer being designed to operate at a first clock cycle time, comprising the steps of:

• providing a cache memory having a faster access time than an access time of said main memory used by said computer;
• permanently disabling or disconnecting said first microprocessor on or before power-up;
• producing a second clock having a faster cycle time than said first clock cycle time;
• providing a second microprocessor operating at said second clock cycle time;
• storing a portion of the data of said main memory in said cache memory;
• intercepting an addressing of a location in said main memory on said address bus by said fast microprocessor;
• producing a signal designating one of a plurality of banks of said main memory in response to the addressing of a location in said main memory by said second microprocessor, each of said banks using the same addresses from said second microprocessor;
• storing, in a tag memory, a first portion of each of the main memory addresses for data also stored in said cache memory, said data being stored in said cache memory at a location in said cache memory corresponding to a second portion of said main memory address;
• comparing a first portion of a current address to said address first portion stored in said tag memory;
• retrieving said data from said cache memory if said compared addresses are identical;
• and
• communicating with said plurality of devices, excluding said first microprocessor, at said first clock cycle time.

An apparatus for enhancing the speed of operation of a computer having a plurality of devices including a first microprocessor and a main memory, said computer being designed to operate at a first clock cycle time, comprising:

• means for coupling said apparatus to address and data lines coupled to said first microprocessor and permanently disabling said first microprocessor on or before power-up;
• means for communicating with said plurality of devices, excluding said first microprocessor, at said first clock cycle time;
• means for producing a second clock having a faster cycle time than said first clock cycle time;
• a cache memory having a faster access time than an access time of said main memory used by said computer;
• a second microprocessor operating at said second clock cycle time;
• means for storing a portion of the data of said main memory in said cache memory;
• means for producing a signal designating one of a plurality of banks of said main memory in response to the addressing of a location in said main memory by said second microprocessor, each of said banks using the same addresses from said second microprocessor;
• means for determining, in response to the addressing of a location in said main memory by said second microprocessor, whether the data of said location is stored in said cache memory;
• and
• means for retrieving said data for said second microprocessor from said cache memory using said second clock if said data are determined to be in said cache memory.

An add-on apparatus for enhancing the speed of operation of a computer having a plurality of devices including a first microprocessor and a main memory, said computer being designed to operate at a first clock cycle time, comprising:

• means for coupling said apparatus to a first address bus and first data bus coupled to said first microprocessor and permanently disabling said first microprocessor on or before power-up;
• means for communicating with said plurality of devices, excluding said first microprocessor, at said first clock cycle time;
• means for producing a second clock having a faster cycle time than said first clock cycle time;
• a second microprocessor operating at said second clock cycle time;
• a cache memory having a faster access time than an access time of said main memory of said computer, said cache memory being smaller than said main memory;
• a tag memory for storing a first portion of each main memory address for data also stored in said cache memory, said first address portion being stored in said tag memory at an address corresponding to a second portion of said main memory address;
• a comparator for comparing a first portion of a current address with a first address portion stored in said tag memory;
• control means for retrieving data for said second microprocessor from said cache memory at said faster access time responsive to said comparator;
• a fast data bus, internal to said add-on apparatus, coupled to said second microprocessor and said cache memory;
• a fast address bus, internal to said add-on apparatus, coupled to said second microprocessor, said tag memory and said comparator;
• means for producing a signal designating one of a plurality of banks of said main memory in response to the addressing of a location in said main memory by said second microprocessor, each of said banks using the same addresses from said second microprocessor;
• a first buffer means for coupling said fast data bus to said first data bus of said first microprocessor;
• and
• a second buffer means for coupling said fast address bus to said first address bus of said first microprocessor.