US 4,794,517 AGranted

Three phased pipelined signal processor

AssigneeInternational Business Machines Corporation

InventorsGardner D. Jones, Larry D. Larsen, Daniel J. Esteban

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Abstract

This processor is a single chip implementation of an architecture that is designed to expeditiously handle certain tasks commonly associated with signal processing. Sequential multiply and accumulate operations, in particular, can be accomplished quite efficiently. The processor is pipelined in two areas. Instructions are passed through a three phase pipeline and consist of fetch, decode and execute, while the multiplier utilizes a two phase pipeline. The data flow is parallel and of 16-bit width throughout. The instruction store is maintained separately from the data store and provisions are included for having the processor enabled to read and write its own instruction store. Some parallel or compound instructions are implemented to permit transfer actions such as storage or I/O to or from instruction registers to occur concurrently with a compute action in different segments of the data flow. The arithmetic capabilities of the processor include both the separate multiplier and a full arithmetic logic unit. Two DMA modes are permitted. Extensive diagnostic capabilities, some of which utilize the processor's ability to read and write its own instruction store, are also included.

Claims1

Dependent claims

An improved pipelined instruction processor comprising a system clock, a working register file, an instruction store, instruction decoding means, an arithmetic computation and logic unit, a multiplier and interconnecting data and instruction busses for directing digital data to said register file, to said arithmetic and logic unit and to said multiplier for controlling said arithmetic and logic unit and said multiplier in response to interrupts and executed instructions characterized in that:

said arithmetic and logic unit, said multiplier and said register file are interconnected via said busses, instructions from said instruction store being decoded in said instruction decoding means;
and
said system clock is connected to synchronize said arithmetic and logic unit to execute a decoded said instruction from said instruction store simultaneously with the decoding of a succeeding instruction therefrom and simultaneously with the feeding of a second succeeding instruction therefrom;
said register file is comprised of a plurality of full word registers arranged to be independently written or read in half-word portions;
during any cycle of said clock, the input of any said registers in said plurality is electively connected to said data bus for storing data there into and output of one of said registers in said plurality is selectively connected to one of said arithmetic and logic unit, said multiplier, and said data bus for outputting data thereto.

2 more elements

Dependencies are inferred from the claim text.

Facts

Application: 06/723,991Filed 15 Apr 1985
Granted: 27 Dec 1988
Term ends: Not estimatedThe source records don’t support an estimate.

Classification4 codes

G06F 9/3889
Using a plurality of independent parallel functional units: controlled by multiple instructions, e.g. MIMD, decoupled access or execute
G06F 9/3861
Concurrent instruction execution, e.g. pipeline or look ahead: recovery, e.g. branch miss-prediction, exception handling
G06F 17/10
Digital computing or data processing equipment or methods, specially adapted for specific functions: complex mathematical operations
G06F
Computing and data processing