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US 4,794,275 AGranted
Multiple phase clock generator
AssigneeTektronix, Inc.
InventorEinar O. Traa
Life of this patent
Estimating the term…
Abstract
A multiple phase clock generator includes a ring of an even number of phase cells, each phase cell generating a separate phased clock signal. Each phase cell supplies its phased clock signal and a prebias output signal in response to concurrent assertion of an enable signal and a prebias output signal from a preceding phase cell on the ring. Enable signals supplied to each phase cell around the ring are asserted and deasserted in response to state changes in a master clock signal, enable signals supplied to non-adjacent phase cells being provided concurrently. When initialized with one phase cell asserting its phased clock signal and prebias output signal, each transition of the master clock signal causes a next phase cell on the ring to supply its phased clock output signal.
Claims18
A multiple phase clock generator for producing a plurality of phased clock signals in response to a master clock signal, the multiple phase clock generator comprising:
- enabling means for alternatively asserting a first and a second enable signal in response to changes in state of said master clock signal;
- a plurality of odd phase cells each providing a separate one of said plurality of phased clock signals and a separate prebias output signal in response to concurrent assertion of said first enable signal and a prebias input signal;
- and
- a plurality of even phase cells each providing a separate one of said plurality of phased clock signals and a separate prebias output signal in response to concurrent assertion of said second enable signal and a prebias input signal,
- wherein said even and odd phase cell are connected to form a ring having odd phase cells interposed between even phase cells, the prebias output signal produced by each odd phase cell is provided as the prebias input signal to a next even phase cell of the ring, and the prebias output signal produced by each even phase cell is provided as the prebias input signal to a next odd phase cell of the ring, and
- wherein at least one of said even and odd phase cells comprises first means for asserting a control signal in response to concurrent assertion of a prebias input signal to said cell and an enable signal and in response to concurrent assertion of the enable signal and a feedback signal, and second means for asserting the feedback signal, the phased clock, and a prebias output signal when said control signal is asserted.
3 more elements
A multiple phase clock generator for producing a plurality of phased clock signals in response to a master clock signal and a reset signal, the multiple phase clock generator comprising:
- enabling means for alternatively asserting a first and a second enable signal in response to changes in state of said master clock signal, said enabling means including means for deasserting both said first and second enable signals in response to assertion of the reset signal;
- a plurality of odd phase cells each asserting a separate one of said plurality of phased clock signals and a separate prebias output signal in response to concurrent assertion of said first enable signal and a prebias input signal;
- and
- a plurality of even phase cells each asserting a separate one of said plurality of phased clock signals and a separate prebias output signal in response to concurrent assertion of said second enable signal and a prebias input signal,
- wherein said even and odd phase cells are connected to form a ring having odd phase cells interposed between even phase cells, the prebias output signal produced by each odd phase cell is provided as the prebias input signal to a next even phase cell of the ring, and the prebias output signal produced by each even phase cell is provided as the prebias input signal to a next odd phase cell of the ring, and
- wherein at least one of said even and odd phase cells comprises first means for asserting a control signal in response to concurrent assertion of a prebias input signal to said cell and an enable signal and in response to concurrent assertion of the enable signal and a feedback signal, and second means for asserting the feedback, signal, the phased clock, and a prebias output signal when said control signal is asserted.
3 more elements
A multiple phase clock generator for producing a plurality of phased clock signals in response to a master clock signal, the multiple phase clock generator comprising:
- means for producing a first current;
- switch means responsive to the master clock signal for alternately providing the first current as an asserted first enable signal and an asserted second enable signal;
- a plurality of odd phase cells each producing one of said plurality of phased clock signals, a separate prebias output signal, and a separate feedback signal, each of the odd phase cells comprising:
- first means for asserting a control signal in response to concurrent assertion of the first enable signal and a prebias input signal, and in response to concurrent assertion of the first enable signal and its feedback signal;
- and
- second means for asserting the feedback signal, the prebias output signal and the phased clock signal when the control signal is asserted;
- and
- a plurality of even phase cells each producing one of said plurality of phased clock signals, a separate prebias output signal, and a separate feedback signal, each of the odd phase cells comprising:
- first means for asserting a control signal in response to concurrent assertion of the second enable signal and a prebias input signal, and in response to concurrent assertion of the second enable signal and its feedback signal;
- and
- second means for asserting the feedback signal, the prebias output signal and the phased clock signal when the control signal is asserted,
- said even and odd phase cells being connected to form a ring wherein the prebias output signal produced by each odd phase cell is provided as the prebias input signal to a next even phase cell of the ring, and the prebias output signal produced by each even phase cell is provided as the prebias input signal to a next odd phase cell of the ring.
9 more elements
A phase cell for producing a phased clock signal comprising:
- first means for asserting a control signal in response to concurrent assertion of a prebias input signal to said cell and an enable signal, and in response to concurrent assertion of the enable signal and a feedback signal;
- and
- second means for asserting the feedback signal, the phased clock, and a prebias output signal when said control signal is asserted.
A multiple phase clock generator comprising:
- a ring of phase cells, each phase cell asserting a separate phased clock output signal and a separate prebias output signal in response to concurrent assertion of an enable input signal and a prebias output signal from a preceding phase cell on the ring;
- and
- means for supplying enable signals to each phase cell around the ring, said enable signals being asserted and deasserted in response to state changes in a master clock signal, enable signals supplied to non-adjacent phase cells being asserted concurrently such that only one phase cell asserts its phased clock output signal at a time and such that each transition of the master clock signal causes a next phase cell on the ring to assert its phased clock output signal,
- wherein at least one of said phase cells comprises first means for asserting a control signal in response to concurrent assertion of a prebias input signal to said cell and an enable signal and in response to concurrent assertion of the enable signal and a feedback signal, and second means for asserting the feedback signal, the phased clock, and a prebias output signal when said control signal is asserted.
1 more element
A multiple phase clock generator for producing a plurality of phased clock signals in response to a master clock signal, the multiple phase clock generator comprising:
- enabling means for alternatively asserting a first and a second enable signal in response to changes in state of said master clock signal;
- a plurality of odd phase cells each providing a separate one of said plurality of phased clock signals and a separate prebias output signal in response to concurrent assertion of said first enable signal and a prebias input signal;
- and
- a plurality of even phase cells each providing a separate one of said plurality of phased clock signals and a separate prebias output signal in response to concurrent assertion of said second enable signal and a prebias input signal,
- wherein one of said even and odd phase cells comprises:
- first means for asserting a control signal in response to concurrent assertion of the prebias input signal to said cell and one of said first and second enable signals, and in response to concurrent assertion of said one enable signal and a feedback signal;
- and
- second means for asserting the feedback signal, and the phased clock and prebias output signals of said cell when said control signal is asserted,
- wherein said even and odd phase cells are connected to form a ring having odd phase cells interposed between even phase cells,
- wherein the prebias output signal produced by each odd phase cell is provided as the prebias input signal to a next even phase cell of the ring, and
- wherein the prebias output signal produced by each even phase cell is provided as the prebias input signal to a next odd phase cell of the ring.
8 more elements
A multiple phase clock generator for producing a plurality of phased clock signals in response to a master clock signal, the multiple phase clock generator comprising:
- means for producing a first current;
- switch means responsive to said master clock signal for alternately directing said first current as asserted first and second enable signals;
- a plurality of odd phase cells each providing a separate one of said plurality of phased clock signals and a separate prebias output signal in response to concurrent assertion of said first enable signal and a prebias input signal;
- and
- a plurality of even phase cells each providing a separate one of said plurality of phased clock signals and a separate prebias output signal in response to concurrent assertion of said second enable signal and a prebias input signal,
- wherein said even and odd phase cells are connected to form a ring having odd phase cells interposed between even phase cells,
- wherein the prebias output signal produced by each odd phase cell is provided as the prebias input signal to a next even phase cell of the ring, and
- wherein the prebias output signal produced by each even phase cell is provided as the prebias input signal to a next odd phase cell of the ring.
5 more elements
A multiple phase clock generator for producing a plurality of phased clock signals in response to a master clock signal and a reset signal, the multiple phase clock generator comprising:
- means for producing a first current;
- switch means responsive to said master clock signal and said reset signal for alternately directing said first current as asserted first and second enable signals when the reset signal is deasserted, and for deasserting the first and second enable signals when the reset signal is asserted;
- a plurality of odd phase cells each asserting a separate one of said plurality of phased clock signals and separate prebias output signal in response to concurrent assertion of said first enable signal and a prebias input signal;
- and
- a plurality of even phase cells each asserting a separate one of said plurality of phased clock signals and a separate prebias output signal in response to concurrent assertion of said second enable signal and a prebias input signal,
- wherein said even and odd phase cells are connected to form a ring having odd phase cells interposed between even phase cells,
- wherein the prebias output signal produced by each odd phase cell is provided as the prebias input signal to a next even phase cell of the ring, and
- wherein the prebias output signal produced by each even phase cell is provided as the prebias input signal to a next odd phase cell of the ring.
5 more elements
Dependencies are inferred from the claim text.