Data processing system with extended memory access

In a data processing system having a dynamic random access memory (DRAM) and a plurality of memory access devices each having a characteristic operating speed, wherein a memory access device outputs control signals for accessing said DRAM and reading data therefrom during a read cycle, a system for maintaining DRAM access by a memory access device until termination of said read cycle comprising:

• control means coupled to the DRAM and said memory access devices and responsive to the control signals output by a memory access device for providing a READ signal to the DRAM, wherein said READ signal is characterized as having a leading edge defining the start of said read cycle and a trailing edge defining the end of said read cycle and wherein said READ signal varies in length in accordance with the duration of said read cycle, said control means further outputting first and second address strobe signals of fixed length having leading and trailing edges fixed in time with respect to the leading edge of said READ signal;
• circuit means coupled to said DRAM and further coupled to said control means and responsive to said READ and second address strobe signals for providing a third address strobe signal to said DRAM, wherein said third address strobe signal is of variable length and includes a leading edge fixed in time with respect to the leading edge of said READ signal and a trailing edge coincident with the trailing edge of said READ signal for providing address information to said DRAM until the end of a read cycle;
• and
• feedback means for comparing the occurrence of said third variable length address strobe signal with the occurrences of said READ signal and said second address strobe signal and for outputting said third variable length signal after said second address strobe signal terminates and so long as said READ signal is asserted.