Single rail CMOS register array and sense amplifier circuit therefor

A storage cell for use in a register array comprising:

• A. write input means for connection to a write data bus and to receive a write enabling signal for selectively coupiing an input data signal from the write data bus to an input node in response to the write enabling signal;
• B. flip-flop means having a forward cell inverter and a reverse cell inverter each having an input terminal and an output terminal, the input terminal of said forward cell inverter and the output terminal of the reverse cell inverter both being connected to the input node, and the input terminal of said reverse cell inverter and the output terminal of said forward cell inverter both being connected to an output node, the reverse cell inverter having a weak current driving capacity to minimize the level of a signal required at said input node from said write input means to drive said forward cell inverter to a desired condition;
• and
• C. a first read output means connected to the output terminal of said flip-flop means and for connection to a first read data bus and to receive a first read enabling signal for selectively coupling the output of said forward cell inverter from the output terminal of said forward cell inverter to the first read data bus in response to the first read enabling signal, and a second read output means for connection to a second read data bus and to receive a second read enabling signal and connected to the output terminal of said forward cell inverter for selectively coupling the output of said forward cell inverter from the output terminal of said forward cell inverter to the second read data bus in response to the second read enabling signal.