Dynamic semiconductor memory with smaller memory cells

A method of operating a dynamic semiconductor memory, said memory comprising

• a first bit line and second bit line for input and output of information, said first and second bit lines being complementary to each other, and
• a plurality of memory cells, each including a selecting means for specifying said memory cell, and a storage capacitor means for storing information, said storage capacitor means having a first terminal connected to said first bit line through said selecting means and a second terminal connected to said second bit line, said first terminal and said selecting means defining a node therebetween,
• said method comprising the steps of
• precharging both said first and second bit lines to the level of a source voltage during a precharge period,
• selecting one of said memory cells by causing said selecting means to electrically connect said first terminal to said first bit line,
• writing a first logic in said selected memory cell by applying said source voltage to said first bit line and ground potential to said second bit line after said precharge period and electrically disconnecting said storage capacitor means from said first bit line, thereby causing the potential of said node to rise to nearly twice said source voltage, or writing a second logic in said selected memory cell by applying ground potential to said first bit line and said source voltage to said second bit line after said precharge period and electrically disconnecting said storage capacitor means from said first bit line, thereby causing the potential of said node to remain at ground potential.