Method and apparatus for temporarily storing multiple data records

A system for transferring a data record of an unspecified bit length into or out of a cache memory coupled between a host computer and a data storage device, whereby valid data including other such data records contained within the cache memory is incapable of being overwritten by a transferring of the data record into the cache memory, comprising:

• cache manager measn, including a microprocessor and microporcessor bus means, for controlling the cache memory;
• first register means coupled between said microprocessor bus means and the cache memory for storing start-of-record address, said start-of-record address defining an address within the cache memory beyond which new data cannot be stored without ovewwriting the valid data;
• second register means coupled between said microprocessor bus means and the cache memory for storing a fill address;
• third reigster means coupled between said microprocessor bus means and the cache memory for storing a drain address;
• means, coupled to said second and third register means, for incrementing said fill and drain addresses stored therein, said fill address contained in said second register means being incremented as each bit of data contained within the data record to be transferred into the cache memory is transferred into the cache memory, each such incrementation yielding a new fill address, and said drain address contained in said third register means being incremented as each bit of data contained within the data record to be transferred out of the cache memory is transferred out of the cache memory, each such incrementation yielding a new drain address;
• means, coupled to said first, second, and third register means, for selectively comparing said start-of-record, fill, and drain addresses stored therein, said comparing means comparing, during transfer of the data record into the cache memory, said fill address contained in said second register means to a selected one of either said start-of-record address contained in said first register means or said drain address contained in said third register means, and, during transfer of the data record out of the cache memory, to said drain address contained in said third register means, whereupon a first indication is sent from said comparing means to the host computer, during transfer of the data record into the cache memory, that a buffer full condition exists either when said fill address contained in said second register means is equal to said start-of-record address contained in said first register means or to said drain address contained in said third register means, or a second indication is sent from said comapring means to the host computer, during a transfer of the data record out of the cache memory, that a buffer empty condition exists when said fill address contained in said second register means is equal to said drain address contained in said third register means;
• means for generating a cyclic redundancy check character for input to the cache memory appended to the data record being transferred into the cache memory;
• means for generating a STOP bit for input to the cache memory appended to said appended cyclic redundancy check character;
• and
• data bus means coupling the host computer, data storage device, and cache memory for trnasfer of data therebetween.