Storage controller emulator providing transparent resource sharing in a computer system
Assignee516277 Ontario Limited
InventorsWilliam M. Maclean, Edward G. Agnew, Richard C. Madter
Life of this patent
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Abstract
A microprocessor controlled mass storage controller is used as an interface for mass storage devices which are shared by a plurality of stand-alone microcomputer systems. The microprocessor controlled mass storage controller has a system interface which maintains communications with a host microcomputer; a dedicated microprocessor which maintains the internal control of the controller and a network interface which maintains an access to the external network. Data transparency and integrity are achieved through the simulation by the controller of the mass storage device characteristics and responses.
Claims6
A microprocessor controlled mass storage controller simulator for coupling a single microprocessor functioning as a central processing unit in a host microcomputer system, the host system normally being coupled by a mass storage controller to a local resource memory means, to a network having at least one network resource memory means connected to means for transmitting and receiving data from the mass storage controller simulator comprising
- a system interface for transferring input and output commands and data to and from the host microcomputer system, such commands and data normally being used by the mass storage controller to control operation of the local resource memory means, said system interface comprising a control interface module coupled to a data transceiver module and the host microcomputer system to generate control signals for the host microcomputer system, and a register bank coupled to said control interface module to provide storage for simulating a mass storage device status, said register bank module comprising a tristate floppy data latch coupled to a peripheral data interface and said data transceiver module, and a printer tristate status buffer coupled to said peripheral data interface and said data transceiver module;
- a dedicated microprocessor coupled to the system interface for emulating the interface between the microcomputer system and the mass storage controller by receiving the input and output commands and data from the host microcomputer system and generating responses thereto in the same manner as the mass storage controller;
- and
- a network interface coupled to said dedicated microprocessor and coupled with the network means for transmitting and receiving data to transfer data to and from the network resource memory means in response to commands from the dedicated microprocessor.
A microprocessor controlled mass storage controller simulator for coupling a single microprocessor functioning as a central processing unit in a host microcomputer system, the host system normally being coupled by a mass storage controller to a local resource memory means, to a network having at least one network resource memory means connected to means for transmitting and receiving data from the mass storage controller simulator comprising
- a system interface for transferring input and output commands and data to and from the host microcomputer system, such commands and data normally being used by the mass storage controller to control operation of the local resource memory means, said system interface comprising a control interface module coupled to a data transceiver module and the host microcomputer system to generate control signals for the host microcomputer system, and a register bank coupled to said control interface module to provide storage for simulating a mass storage device status, said register bank comprising a floppy control latch coupled to a peripheral select interface and said control interface module, a two-to-one floppy data selector buffer coupled to said peripheral select interface and said control interface module;
- and a two-to-one floppy status selector buffer coupled to said peripheral select interface and the control interface module in which the two-to-one selector buffers are responsive to signals generated by the dedicated microprocessor and the control interface module;
- a dedicated microprocessor coupled to the system interface for emulating the interface between the host microcomputer system and the mass storage controller by receiving the input and output commands and data from the host microcomputer system and generating responses thereto in the same manner as the mass storage controller;
- and
- a network interface coupled to the said dedicated microprocessor means and coupled with the network means for transmitting and receiving data to transfer data to and from the network resource memory means in response to commands from the dedicated microprocessor means.
A microprocessor controlled mass storage controller simulator for coupling a single microprocessor functioning as a central processing unit in a host microcomputer system, the host system normally being coupled by a mass storage controller to a local resource memory means, to a network having at least one network resource memory means connected to means for transmitting and receiving data from the mass storage controller simulator comprising
- a system interface means for transferring input and output commands and data to and from the host microcomputer system, such commands and data normally being used by the mass storage controller to control operation of the local resource memory means;
- a dedicated microprocessor means coupled to the system interface means for emulating the interface between the microcomputer system and the mass storage controller by receiving the input and output commands and data from the microcomputer system and generating responses thereto in the same manner as the mass storage controller, said dedicated microprocessor means comprising a microprocessor chip for executing instructions, a Random Access Memory (RAM) means for buffering data to be transferred between the system interface and the network interface and for storing temporary control information;
- control circuitry for generating control and select signals to selectively coordinate the operation of the dedicated microprocessor with the RAM, system interface and network interface, and a clock generating circuitry coupled to said control circuitry for controlling data transfers of the dedicated microprocessor;
- and
- a network interface coupled to the dedicated microprocessor means and coupled with the network means for transmitting and receiving data to transfer data to and from the network resource memory means in response to commands from the dedicated microprocessor means.
Dependencies are inferred from the claim text.