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US 4,792,841 AGranted
Semiconductor devices and a process for producing the same
AssigneeHitachi, Ltd.
InventorsKouichi Nagasawa, Yoshio Sakai, Osamu Minato, Toshiaki Masuhara, Satoshi Meguro
Life of this patent
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Abstract
Disclosed is an MOSIC including a plurality of silicon gate type MOSFET's in which, after the polycrystalline silicon wirings are formed simultaneously with polycrystalline silicon gates, electrodes contacted with the source and drain regions are made of polycrystalline silicon so as to be connected to the polycrystalline silicon wirings, thereby to prevent the shallow pn junctions of the source and drain regions from being destroyed by the contacts and to provide a high degree of integration to one silicon chip.
Claims29
A static random access memory semiconductor device formed on a semiconductor material comprising:
- a word line extending over said semiconductor material;
- a pair of data lines extending over said semiconductor material;
- a power supply line extending over said semiconductor material;
- a peripheral circuit comprising complementary MISFETs;
- and
- at least one memory cell fabricated in a surface region of said semiconductor material, said memory cell including first, second, third and fourth transistors, and a pair of load resistors, each of said transistors being of an insulated gate field effect type and having source and drain semiconductor regions formed in said semiconductor material and a gate;
- each of said gates of said first and second transistors being electrically connected to said drain semiconductor region of the other of said first and second transistors;
- one of said pair of load resistors being connected between the drain semiconductor region of said first transistor and said power supply line, and the other of said pair of load resistors being connected to the drain semiconductor egion of said second transistor and said power supply line;
- said third transistor being electrically coupled between said drain semiconductor region of said first transistor and one of said pair of data lines so that a current path from the source semiconductor region of the third transistor to the drain semiconductor region of the third transistor is formed between said drain semiconductor region of the first transistor and said one of said pair of data lines, said gate of said third transistor being formed as a part of said word line;
- said fourth transistor being electrically coupled between said drain semiconductor egion of said second transistor and the other of said pair of data lines so that a current path from the source semiconductor region of the fourth transistor to the drain semicondcutor region of the fourth transistor is formed between said drain semiconductor region of said second transistor and the other of said pair of data lines, said gate of said fourth transistor being formed as another part of said word line;
- said gates of said first and second transistors being respectively formed in first and second strips, of electrically conducting materials of a first level, which are extended on an insulating film formed over said semiconductor material;
- said power supply line being formed of a third strip, of polycrystalline silicon of a second level, which is extended on an insulating film formed over said semiconductor material;
- and
- said pair of load resistors being respectively formed in polycrystalline silicon of the second level as branches of said third strip, said polycrystalline silicon of the second level as branches of said third strip is formed integrally with said third strip forming said power supply line.
11 more elements
A static random access memory semiconductor integrated circuit device comprising:
- a semiconductor material of a first type of conductivity having a surface;
- a well region of a second type of conductivity, opposite to the first type of conductivity, which is selectively formed in a surface region of said semiconductor material, said well region having at least one memory cell provided therein, said at least one memory cell including MISFETs, the MISFETs having source and drain regions;
- semiconductor elements provided in a surface region of said semiconductor material, wherein the semiconductor elements provided in the surface region of said semiconductor material form a peripheral circuit for said at least one memory cell, said peripheral circuit having source and drain regions formed in the semiconductor material, the semiconductor elements forming the peripheral circuit including complementary MISFETs;
- at least one of said peripheral circuit and each of the memory cells including a first conductor layer, wherein the source and drain regions, of said at least one of said peripheral circuit and the memory cells including a first conductor layer, are formed in self-alignment with said first conductor layer;
- a second conductor layer constituting a wiring for said at least one of said peripheral circuit and the memory cells, the second conductor layer forming load resistors of the memory cells and a power supply line, whereby the load resistors and power supply line are integrally formed;
- and
- a third conductor layer, of metal, constituting a wiring for said at least one of said peripheral circuit and the memory cells, the third conductor layer being disposed over the second conductor layer.
4 more elements
A static random access memory semiconductor integrated circuit device comprising:
- a semiconductor material of a first type of conductivity having a surface;
- a well region of a second type of conductivity opposite to the first type of conductivity, which is selectively formed in a surface region of said semiconductor material, said well region having at least one memory cell provided therein, said at least one memory cell including MISFETs, the MISFETs having source and drain regions;
- semiconductor elements provided in a surface region of said semiconductor material, wherein the semiconductor elements provided in the surface region of said semiconductor material form a peripheral circuit for said at least one memory cell, said peripheral circuit having source and drain regions formed in the semiconductor material, the semiconductor elements forming the peripheral circuit including complementary MISFETs;
- at least one of said peripheral circuit and each of the memory cells including a first conductor layer, wherein the source and drain regions, of said at least one of said peripheral circuit and the memory cells including a first conductor layer, are formed in self-alignment with said first conductor layer;
- a second conductor layer constituting a wiring for said at least one of said peripheral circuit and the memory cells, the second conductor layer forming load resistors of the memory cells and a power supply line, whereby the load resistors and power supply line are integrally formed;
- a third conductor layer formed above said semiconductor material;
- and
- wherein said second conductor layer is formed to contact one of said source and drain regions of said peripheral circuit and each of said memory cells and to contact said third conductor layer, to provide electrical connection between said one of said source and drain regions and said third conductor layer.
5 more elements
A static random access memory semiconductor integrated circuit device comprising:
- a semiconductor material of a first type of conductivity having a surface;
- a well region of a second type of conductivity, opposite to the first type of conductivity, which well region is selectively formed in a surface region of said semiconductor material, said well region having at least one memory cell provided therein, said at least one memory cell including MISFETs, the MISFETs having source and drain regions;
- semiconductor elements provided in a surface region of said semiconductor material, wherein the semiconductor elements provided in the surface region of said semiconductor material form a peripheral circuit for said at least one memory cell, said peripheral circuit having source and drain regions formed in the semiconductor material, the semiconductor elements forming the peripheral circuit including complementary MISFETs;
- and
- at least one of said peripheral circuit and each of the memory cells including a first conductor layer, wherein the source and drain regions, of said at least one of said peripheral circuit and the memory cells including a first conductor layer, are formed in self-alignment with said first conductor layer;
- and
- each of the memory cells including a second conductor layer which serves as load means for each of the memory cells and as a power supply line, whereby the load means and power supply line are integrally formed.
4 more elements
A static random access memory semiconductor integrated circuit device formed on a semiconductor material, comprising:
- a plurality of memory cells, each memory cell having load resistors of polycrystalline silicon and a plurality of MISFETs;
- a peripheral circuit including complementary MISFETs;
- and
- a power supply line extending over the semiconductor material, with one of the load resistors of each memory cell being connected between a drain semiconductor region of one of the MISFETs of the memory cell and said power supply line, and with another of the load resistors of each memory cell being connected between a drain semiconductor region of another MISFET of the memory cell and said power supply line,
- wherein gate electrodes of the MISFETs in each memory cell are made from a first level conductive material layer, and the one and the another of the load resistors, and the power supply line, are made integrally from a second level conductive material layer of polycrystalline silicon.
2 more elements
Dependencies are inferred from the claim text.