Converting numbers between binary and another base

Apparatus for converting a binary operand to decimal, the decimal number being represented as a sequence of at most n BCD digits, for use in association with a data processing system having a plurality of functional units for performing arithmetic and logical operations, having a control means for generating a plurality of control signals to operate the functional units and having a clock signal, the control means updating the control signals once each clock cycle, the apparatus comprising:

• a register having a first group of bits and having an input and an output;
• means for calculating a first product by multiplying the operand by a first multiplicand substantially equal to 10.sup.-m, where m is an integer between 1 and n-1, inclusive, the first product having an integer part and a fractional part, the fractional part being placed in the first group of bits in the regiser prior to a series of m of the clock cycles;
• a combinational adder having a first input coupled to a version of the register output shifted left by one bit, a second input coupled to a version of the first group of bits in the register output shifted left by three bits and an output coupled to the input of the register;
• and
• means for latching the input of the register to the output of the register on each of the series of m of the clock cycles to iteratively generate as the integer part of successive adder outputs the m low-order digits of the decimal number, one digit per clock cycle.

Apparatus operative in a first mode to convert radix-b numbers to binary and in a second mode to convert binary numbers to radix-b, each radix-b number being represented as a sequence of at most n digits occupying c bits each, comprising:

• a convert register having an input and an output;
• combinational computational means having a digit input, for combinationally generating a result equal to the value at the digit input plus b times the value in the convert register, the computational means result being coupled in its entirety to the input of the convert register;
• means for operating the apparatus in the first mode;
• and
• means for operating the apparatus in the second mode.

Apparatus for performing bidirectional conversion of numbers between binary and decimal in response to first and second programmed signals, the decimal number being represented as a sequence of at most 10 BCD digits, for use in association with a high speed data processing system having a plurality of functional units for performing arithmetic and logical operations, having a control means for generating a plurality of control signals to operate the functional units and having a clock signal, the control means updating the plurality of control signals once each clock cycle, the apparatus comprising:

• a convert register having an input and an output and latching the input to the output on each clock cycle, the convert register having a first group of bits in which the binary number is calculated or from which the decimal number is calculated;
• a combinational adder having an output and having a first input coupled to a version of the entire first group of bits in the convert register shifted left by one bit, a second input coupled to a version of the entire first group of bits in the convert register shifted left by three bits and a third input, the output of the adder being coupled unshifted to the input of the convert register with the low-order bit of the first group of bits receiving the low-order bit of the output of the adder;
• an operand register having an output having a high-order nibble, the high-order nibble of the operand register output being coupled right-justified to the third input of the adder;
• means for operating the apparatus to convert a decimal number to binary in response to the first programmed signal, comprising:
• means for preloading the first group of bits in the convert register with zero prior to a first series of the clock cycles;
• means for loading the decimal number into the operand register with the most significant digit of the decimal number in the high-order nibble of the operand register, the loading of the operand register taking place prior to the first series of cycles, the combinational adder thereby providing to the input of the convert register a first intermediate result in response to the values in the convert register and the operand register;
• and
• means for clocking the output of the combinational adder into the convert register after each of the cycles in the first series of cycles and for shifting the value in the operand register by one nibble toward the high-order nibble after each of the cycles in the first series of cycles to thereby iteratively calculate the binary number in the convert register, one decimal digit being converted on each clock cycle in the first series of cycles;
• the apparatus further comprising:
• means for operating the apparatus to convert a binary number to a decimal number in response to the second programmed signals, comprising:
• means for calculating a first product by multiplying the binary number by a first multiplicand substantially equal to 10.sup.-m, 0<m<9, the first product having an integer part and a fractional part, and for subsequently initializing the convert register with the fractional part of the first product left-justified in the first group of bits prior to a second series of the clock pulses;
• means for calculating a second product by multiplying the integer part of the first product by a second multiplicand substantially equal to 10.sup.m-9, the second product having an integer part and a fractional part, and for initializing the convert register with the fractional part of the second product left-justified in the first group of bits prior to a third series of the clock pulses distinct from the second series of the clock pulses;
• means for supplying zero to the third input of the adder for each cycle in the second and third series of cycles;
• and
• means for collecting in sequence the integer part of the second product, the integer part of the output of the adder following each cycle in the third series of cycles, the integer part of the output of the adder following each cycle in the second series of cycles and a sign code to thereby assemble the decimal number.