Phase and frequency detector and use of this detector in a phase-lock loop

Phase and frequency detector, receiving two logic input signals, R and V, comprising a set of 2k+2 memory cells (MU.sub.k to MU.sub.0, and MD.sub.0 to MD.sub.k) which are cascade connected and linked in twos by 2k+1 control cells (CUD.sub.0, CU.sub.01 to CU.sub.k-1,k, CD.sub.01 to CD.sub.k-1,k) capable firstly, of transferring the information, contained in the changes of state of the signals R and V, from the end memory cells (MU.sub.k, MD.sub.k), to which they are respectively applied, and by each direction respectively, up to a memory cell MU.sub.n or MD.sub.n (depending on whether the signal R is in advance or is delayed with respect to the signal V), this memory cell then providing square waves, the duty factor of which is proportionate to the instantaneous phase shift D.phi. between the signals R and V, when (2.pi.-1)n<.vertline.D.phi..vertline.<2n.pi., and secondly, of keeping the memory cells MU.sub.n+1 to MU.sub.k and MD.sub.0 to MD.sub.k in their initial logic state, and cells MU.sub.0 to MU.sub.n-1 in an opposite logic state, or memory cells MD.sub.n+1 to MD.sub.k and MU.sub.0 to MU.sub.k in their initial logic state, and cells MD.sub.0 to MD.sub.n-1 in an opposite logic state, depending on whether the signal R is ahead or delayed with respect to the signal V.