US 4,792,753 AGranted

Local area network protocol analyzer

AssigneeNippon Board Computer Co., Ltd.

InventorKiyoshi Iwai

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Abstract

A local area network protocol analyzer for analyzing packets or signal series running in a coaxial cable of a local area network and comprising a code/decoder to separate a packet received from the coaxial cable into a clock signal and a serial data signal, a receive signal processing section to convert the serial data signal into parallel data, a receive memory section to store the parallel data from the receive signal processing section in a receiving data memory section thereof and an output/input section to analyze and indicate the parallel data in the receiving data memory section and to input instruction signal to instruct the sections therefrom, the receive signal processing section including a control counter for controlling an address where the parallel data is stored in the receiving data memory and being counted up for every storing of the parallel data and the receive memory section including a managing data memory section under control of which a memory address pointer indicating where the packets are stored is set, a packet length is measured and a packet interval is measured.

Claims10

Dependent claims

A local area network protocol analyzer for analyzing packets running in a coaxial cable of a local area network, said analyzer comprising:

an interchangeable code/decoder, said code/decoder being operatively connected to said coaxial cable and adapted to decode a packet received from the coaxial cable into a clock signal and a serial data signal;
a receive signal processing section, said receive signal processing section receiving the serial data signal and adapted to convert the serial data signal into parallel data;
a receive memory section having a receiving data memory section, said receiving data memory section receiving and storing the parallel data from the receive signal processing section;
a receive memory control section, said receive memory control section controlling said code/decoder, said receive signal processing section and sid receive memory section;
a first bus, said first bus communicating with said receive memory control section;
a bus controller, said bus controller communicating with said first bus and said receive memory section;
a second bus, said second bus communicating with said bus controller, wherein said bus controller selectively allows communication between the buses and between the receive memory section;
an output/input section, said output/input section being connected to said second bus and being adapted to display the parallel data in the receiving data memory section and to allow input of instructions to control the analyzer;
a main control section, said main control section communicating with said second bus, whereby all operations of the analyzer may be controlled;
said receive signal processing section including a control counter for controlling an address where the parallel data is stored in the receiving data memory section, said counter counting after each store operation;
and said receive memory section including a managing data memory section under the control of which for each packet a memory address pointer indicating where the packet is stored is maintained, a packet length is measured and a packet time interval is measured whereby the data from said receive data memory section is analyzed relative to the packet length and packet time interval from said managing data memory section.

8 more elements

A protocol analyzer for analyzing packets on a local area network, comprising:

a. an interchangeable code/decoder, said code/decoder translating the packets to a common digital logic form;
b. a filter section having user selectable parameters, said filter section acting on the packets to admit or exclude packets from the analyzer based on said parameters;
c. packet storage means, said packet storage means storing at an address each packet admitted to the analyzer;
d. packet measurement means, said measurement means measuring a length of each packet and a time since the previous packet;
e. measurement storage means, said measurement storage means storing, for each packet admitted, the address, the length and the time since the previous packet;
f. packet control means, said packet control means controlling, for each admitted packet, the operation of said packet storage means, said packet measurement means, and said measurement storage means;
g. main control means, said main control means controlling the code/decoder, the filter section and the packet control means, and being adapted to access the packet storage means and the measurement storage means independently of the packet control means and to generate a statistical measurement of network performance from the packets, lengths and times contained therein;
h. output means, said output means adapted to display the statistical measurement;
and
i. input means, said input means being adapted to allow user control of the main control means and entry of the parameters, whereby said interchangeable code/decoder allows the analyzer to be used on different type networks by user selection of the code/decoder and said access of the packet storage means and the measurement storage means independently of the packet control means speeds up the generation of the statistical measurement.

7 more elements

Dependencies are inferred from the claim text.