Dual transistor output stage

A circuit for conducting current between an input and an output terminal in response to a control signal, said circuit comprising:

• at least first and second transistors, each adapted to conduct current between said input and output terminals, said first transistor adapted to conduct high current at low collector-emitter voltages, and said second transistor adapted to conduct high current at high collector-emitter voltages;
• and
• means for varying the current conducted by each of said first and second transistors,
• whereby, substantially all of the current conducted between said input and output terminals is conducted by said first transistor over a first range of voltage differentials between said input and output terminals, and substantially all of the current conducted between said input and output terminals is conducted by said second transistor over a second range of voltage differentials between said input and output terminals, said second range being higher than the first range.

A circuit for conducting a load current between an input terminal and an output terminal in response to a control signal, said circuit comprising:

• first and second transistors, each having a ballast resistance and each adapted to conduct a current between said input and output terminals, said first transistor having a ballast resistance which is greater than the ballast resistance of said second transistor;
• third and fourth transistors having a common base drive node adapted to receive said control signal;
• means connected to an emitter of said third transistor at a first node and to the base of said first power transistor for providing drive current to the base of said first transistor in response to said control signal when said control signal exceeds a predetermined value;
• means connected to an emitter of said fourth transistor at a second node and to the base of said second transistor for providing drive current to the base of said second transistor in response to said control signal;
• means connected to said first and second nodes for limiting the current conducted by said first and second transistors, whereby said first transistor conducts substantially all of said load current over said first range of voltage differentials and second transistor conducts substantially all of said load current over said second range of voltage differentials.