Coplanar die to substrate bond method
AssigneeMotorola, Inc.
InventorsJames E. Drye, Steven L. Post
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AssigneeMotorola, Inc.
InventorsJames E. Drye, Steven L. Post
Estimating the term…
A method for bonding die to substrates coplanarly in a multichip module assembly. After the die are aligned into die openings of the substrate, a glass slurry is applied and the module is fired to solidify the glass. Because of shrinkage of the glass slurry firing, a groove results between the die and the substrate. To fill on this groove, a polyimide or like film is adhered and then pressed and cured on the surface of the die and substrate. This film is used as a base for interconnect lines.
A method for achieving coplanarity in bonding die to substrates in multichip modules comprising the steps of:
A method for achieving coplanarity in bonding die to substrates in multichip modules comprising the steps of:
Dependencies are inferred from the claim text.
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No related US applications are recorded in the indexed filing history.
Interconnections or connectors in packages: die-attach connectors
Connecting or disconnecting: of die-attach connectors
Of die-attach connectors: connecting techniques
Connecting techniques: using a polymer adhesive, e.g. an adhesive based on silicone or epoxy
Term ended 13 Mar 2007 (estimated)
USPTO file history isn’t available for this patent, so only indexed dates are shown.
This invention generally pertains to a coplanar die to substrate bond method. Generally, in high density integrated circuit module assemblies and the like, it is desirable to have a coplanar relationship between the plurality of die and the substrate in which the die are mounted so that future processing steps may be performed with relative ease. U.S. Pat. No. 4,630,096 entitled "High Density IC Module Assembly" which was issued on Dec. 16, 1986 is the type of module in which the present invention will be used.
Previous die to substrate bond methods have met difficulty in that there is a lack of coplanarity between the die and the substrate. The die are generally bonded to the substrate using a glass slurry. Perhaps the most common problem occurs due to the firing of the glass after it has been applied to the die and substrate. While the glass is being fired, it shrinks, thereby creating grooves between the substrate and the die. This lack of coplanarity creates shorting of interconnect lines and step coverage problems due to improper amounts of metal interconnect being disposed in the existing groove. Therefore, a coplanar die to substrate bonding method which allows easier interconnect line processing steps is highly desirable.
The present invention pertains to a coplanar die to substrate bond method. When using this method, a plurality of die are aligned so that they may be disposed in predetermined die openings in a silicon wafer substrate. Once these die are aligned, a glass slurry is applied so that a bond may be formed between the die and the substrate. After excess glass slurry is cleaned from both the die and the substrate, the module is fired until the glass becomes solid. Commonly, during this firing, the glass shrinks and grooves are formed between the die and the substrate. The elimination of this groove is essential in order to obtain coplanarity on the face of the module. To do this, the applying and firing of the glass slurry may be done more than once. Also, to further reduce the groove, a polyimide adhesive is spun onto the face of the die and substrate and a polyimide film layer will further be disposed on the adhesive. This adhesive and polyimide film layer are pressed and cured thereby covering in the unwanted grooves.
Referring to the drawings, wherein like characters indicate like parts throughout the figures:
FIG. 1 is a highly enlarged top view of a section of a silicon wafer of the type which will embody the present invention;
FIG. 2 is a highly enlarged cross sectional view of a die bonded to a silicon wafer substrate embodying the present invention; and
Referring specifically to FIG. 1, a highly enlarged top view of a section of a silicon wafer substrate, designated 10, and FIG. 2, a highly enlarged cross-sectional view of a die bonded to silicon wafer substrate 10 are shown. Silicon wafer 10 has a first surface, 12, and a second surface, 14. Further, silicon wafer 10 includes a plurality of die openings, 16, which are formed in silicon wafer 10 by etching or other methods well known in the art. Each member of a plurality of die, 18, includes a first surface, 20, and a second surface, 22. Members of plurality of die 18 are disposed throughout silicon wafer 10 in die openings 16. Plurality of die 18 are disposed in die openings 16 of silicon wafer 10 so that first surfaces 20 of plurality of die 18 face in the same direction as first surface 12 of silicon wafer 10 and substantially lie in a common plane. Respectively, second surface 22 of plurality of die 18 face in the same direction as second surface 14 of silicon wafer 10. Plurality of die 18 are disposed and aligned on a vacuum plate which is specially designed so that silicon wafer 10 also may be aligned with respect to plurality of die 18 on the same vacuum plate thereby allowing for a predetermined relationship between silicon wafer 10 and plurality of die 18.
Once plurality of die 18 are disposed and aligned in the predetermined relationship with respect to silicon wafer 10, a slurry of glass, 24, is applied to silicon wafer 10 and plurality of die 18 so as to bond them together. Once glass 24 is applied in slurry form, silicon wafer 10 and plurality of die 18 remain on the vacuum plate until glass 24 hardens slightly. Then silicon wafer 10 and plurality of die 18 are removed and excess glass 24 is cleaned from both the first surface 12 and second surface 14 of silicon wafer 10 as well as first surface 20 and second surface 22 of plurality of die 18. Once this cleaning has been accomplished, silicon wafer 10 and plurality of die 18 are fired so that glass 24 will melt and form a solid bond between silicon wafer 10 and die 18. The temperature at which the firing takes place is determined by the type of glass 24 which is used. Commonly, CF6 Nippon Electric Glass with a 15% SiO.sub.2 filler is used. A predetermined amount of terpineol is used so that the glass may be applied in slurry form. Because glass 24 will have a certain amount of shrinkage when fired it is possible that the process of applying the glass slurry, cleaning and firing be performed more than once.
Following the firing of silicon wafer 10, plurality of die 18 and glass 24, a small groove 32, may still exist due to the shrinkage of glass 24 during firing. Groove 32 will cause many problems in future processing steps some of these problems being step coverage and the shorting of interconnect lines. In order that these problems do not occur, it is desirable to eliminate groove 32 so that first surface 12 of silicon wafer 10 and first surfaces 20 of plurality of die 18 as well as areas in between them are coplanar. The coplanarity is achieved by applying a polyimide or like film to first surface 12 of silicon wafer 10 and first surfaces 20 of plurality of die 18.