High-speed demultiplexer circuit
AssigneeAmerican Telephone and Telegraph Company, AT&T Bell Labs
InventorRobert G. Swartz
Life of this patent
Estimating the term…
Abstract
A demultiplexer for demultiplexing a multiplexed input data signal into M output channels using M sequencer means clocked from an overlapping M phase system clock. The system clock operates at a frequency equal to the input data signal rate divided by M. Each sequencer means is clocked by a unique combination of the M phase system clock signals to select one data channel from the multiplexed input data signal. Since all sequencer means circuits are synchronized to the system clock, no variable delay lines are needed to align the timing between the circuit stages. A time delay latch is provided where needed in each sequencer means to enable all channels to output data concurrently. The demultiplexer includes a real-time data-framing capability to assure that the input data is correctly mapped to the proper output channels.
Claims9
A 1:M demultiplexer apparatus, where M is an integer equal to or greater than 4, for demultiplexing a multiplexed data signal into M data channels, said demultiplexer apparatus comprising:
- means for generating M phase system clock signals at a frequency which is equal to the input data signal rate divided by M;
- and
- M sequencer means for decoding said multiplexed data signal into M data channels, each of said M sequencer means being clocked by a different combination of said M phase system clock signals to select one data channel from said multiplexed data signal.
A 1:2.sup.N (where N is an integer .gtoreq.2) demultiplexer apparatus for demultiplexing a multiplexed digital input data signal into 2.sup.N channels, said demultiplexer apparatus comprising:
- means for generating system clock signals having 2.sup.N phases at a frequency which is equal to an input data signal rate divided by 2.sup.N ;
- and
- 2.sup.N sequence means for decoding said input data signal into 2.sup.N data channels, each of said 2.sup.N sequencer means being clocked by a different combination of said 2.sup.N phase system clock signals to select one data channel from said input data signal.
A 1:2 demultiplexer apparatus for demultiplexing a multiplexed digital input data signal into two channels, said demultiplexer apparatus comprising:
- means for generating a system clock having two phases at a frequency which is equal to one-half of the rate of the input data signal;
- two sequencer means for decoding said multiplexed data signal into two data channels, each of said two sequencer means being clocked by a different phase of said system clock to select one data channel from said multiplexed data signal;
- two channel shifter means, each associated with one of said sequencer means, for changing the channel of data selected by each of said sequencer means in response to a control signal.
Dependencies are inferred from the claim text.