Semiconductor memory device having erroneous write operation preventing function

A semiconductor memory device comprising:

• a first power supply terminal means (V.sub.CC);
• a second power supply terminal means (GND);
• a terminal for receiving a write enable signal (WE);
• an erroneous write operation preventing circuit (16"), connected to said first and second power supply terminal means and to said terminal, for receiving said write enable signal and generating an internal write enable signal (IWE) for an actual write operation only when a potential of said high power supply terminal means is higher than a predetermined value;
• and
• means, connected to said erroneous write operation preventing circuit, for resetting said circuit after receiving said internal write enable signal,
• said erroneous write operation preventing circuit comprising:
• an enhancement-type MIS transistor (Q.sub.11) having a drain connected to said first power supply terminal means, a gate for receiving said write enable signal, and a source;
• a depletion-type MIS transistor (Q.sub.12) having a drain connected to the source of said enhancement-type MIS transistor, and a gate and a source thereof connected to said second power supply terminal means;
• and
• a flip-flop (FF) having a set terminal connected to the drain of said depletion-type MIS transistor, a reset terminal for receiving an output signal from said resetting means, and an output for generating said internal write enable signal.