US 4,791,611 AGranted

VLSI dynamic memory

AssigneeUniversity of Waterloo

InventorsAli G. Eldin, Mohammed I. Elmasry

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Abstract

The disclosed chip is suitable for VLSI dRAMS. The memory cell includes a bipolar transistor, a JFET, and a capacitor. The capacitor comprises a MOSFET which is operated only in the accumulation mode. Each cell requires only three lines. On a p-substrate, which comprises the collector of the bipolar, the cell layers are:- an n-well which comprises the channel of the JFET and the base of the bipolar; a p-region, which comprises the gate of the JFET, the emitter of the bipolar, and the bottom plate of the capacitor; an oxide layer; and a conducting layer; arranged as a vertical stack in that order. The latter two layers are the insulator and the top plate of the capacitor. The source and drain of the JFET are respective n+ regions placed one either side of the stack. The n-well can be deep and hence can be compatible with conventional CMOS technology. The chip has full read, write, and refresh capability; is relatively easily manufactured; and can be considerably scaled down without losing performance.

Claims22

Dependent claims

Dynamic memory or storage cell, for uses in an integrated circuit chip, wherein:

the cell includes a cell-substrate, which is doped to a first polarity of conductivity;
the cell includes a source, a drain, and a channel-diffusion;
the channel-diffusion extends between the source and the drain;
the channel-diffusion is formed as a diffusion into the substrate, and is doped to the opposite polarity of conductivity to the substrate;
the cell includes a gate;
the cell is so arranged and disposed that the channel diffusion is sandwiched between the cell-substrate and the gate, whereby the source, drain, channel-diffuion and gate comprise an opposite-polarity-channel junction-gate field-effect transistor (JFET);
the cell includes an emitter means;
the cell-substrate, the channel-diffusion, and the emitter means are so arranged and disposed in the cell as to comprise the collector, base, and emitter respectively of a bipolar transistor;
the cell includes an upper plate, a lower plate, and an insulation means for insulating the two plates;
the plates and the insulation means are so arranged and disposed in the cell as to comprise a capacitor;
and the cell includes a voltage-equalizing means for maintaining the gate, the emitter means, and the lower plate always at the same voltage as each other.

8 more elements

Dependencies are inferred from the claim text.