Dynamically reconfigurable array logic

A dynamically reconfigurable array logic comprising:

• a RAM programmable logic array comprising an array of bits, each bit comprising a fuse connection between logic elements;
• I/O means coupled to the RAM programmable logic array for logical selection of a registered output;
• first register means coupled to the RAM programmable logic array for receiving data and high level commands;
• a pair of up/down counters coupled to the RAM programmable logic array;
• timing means coupled to the RAM programmable logic array for issuing READ and WRITE strobes;
• and
• bus means for coupling control signals between said RAM programmable logic array, said first register means and second register means;
• said second register means coupled to the RAM programmable logic array for functioning as a comparator in a first mode and for functioning to load outputs during specified time intervals in a second mode, said second register means responsive in said first mode to said control signals from said first register means and to output signals from said I/O means, for comparing said control signals and said output signals and for providing portions of said control signals to said RAM programmable logic array when said compared signals are equal, thereby to reconfigure said logic array.

A dynamically reconfigurable array logic comprising:

• A RAM programmable logic array comprising an array of bits, each bit comprising a fuse connection between logic elements;
• I/O means coupled to the RAM programmable logic array for logical selection of registered output;
• first register means coupled to the RAM programmable logic array for receiving data and high-level commands;
• sequencer means, including a pair of up/down counters, coupled to the RAM programmable logic array for generating addresses;
• timing means coupled to the RAM programmable logic array for controlling DMA transfers and for issuing READ and WRITE strobes;
• and
• bus means for coupling control signals between said RAM programmable logic array, said first register means, and second register means;
• said second register means coupled to the RAM programmable logic array for monitoring outputs and for functioning as a comparator in a first mode and for functioning to load outputs during specified time intervals in a second mode, said second register means responsive in said first mode to control signals from said first register means and to output signals from said I/O means, for comparing said control signals and said output signals and for providing portions of said control signals to said RAM programmable logic array when said compared signals are equal, thereby to reconfigure said logic array.