US 4,791,602 A · Soft programmable logic array

Abstract

A programmable logic array is constructed of independently controllable logic building blocks of two types and special output logic to perform desired logic functions. The first building block is a functional element which is capable of performing any logical function of its input data to create output data. The functional elements shown are based on three inputs with a single output. The second basic type of building block is a pass-through/hold device which may either pass its input directly through as an output, or which may latch and hold the input until clocked. A plurality of logic levels or ranks of elements of the first type and ranks of the second type are interconnected so that the output can be various functions of the inputs. The logic array described here has first and second logic levels consisting of functional elements followed by a third level of pass-through/hold devices. The fourth and fifth logic levels are functional elements and pass-through/hold devices. The seventh and eighth logic levels are represented by another level of functional elements and pass-through/hold devices. Finally, the output logic is a plurality of output enable gates connected to tri-state buffers. The tri-state buffers may be high, low or floating. The output enable gate functions to either cause a direct pass-through of the input logic signal or activates the tri-state buffer to operate on the output logic level. The logic array is configured and controlled by input control bits to characterize the operation of each functional element and pass-through/hold device so that it functions either to produce combinations of input logic levels or to achieve particular logic states or a combination of the two functional modes. The output enable gates are controlled like the functional elements to either enable or disable tri-state control of the output buffers.

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Claims26

Dependent claims

A soft programmable logic array for selectively providing every possible function for operating on a set of data input thereto such that any one of said possible functions may be performed in a single pass, having:

an output,
a plurality of logic ranks each rank having logic inputs, data inputs, and data outputs which are a predetermined function of the inputs, each logic rank being formed of a plurality of configurable functional element means wherein each functional element means has inputs connected to receive data inputs and logic inputs connected to receive configuration logic inputs and outputs connected to provide data output which is the solution to a logic equation (operated on the data inputs) determined by the set of logic inputs received by that functional element means, each of said functional element means also having a plurality of latches equivalent to the number of possible output states for holding a predetermined logic indication of the associated output state corresponding to the logic function implemented,
a plurality of ranks of flip-flop pass-throughs having an input connected to receive a configuration logic datum, in each said rank a flip-flop pass-through is paired to a functional element means, a flip-flop pass-through having an input connected to receive the data output of that one of said logic rank's functional element means and a flip-flop pass-through also having an output connected to a data input of at least one of the functional element means in the succeeding logic rank and connected to the output of said logic array wherein each said flip-flop pass-through may invert a logic condition and pass that condition through without delay or latch a logic condition until released, depending on the configuration logic datum supplied thereto, and
control means for setting all of said functional elements and flip-flop pass-throughs with individual configuration logic data to cause the array to perform a predetermined logic function on the data input,
wherein the output of each functional element in each preceding logic rank is provided as one input to at least one functional element of a succeeding logic rank and at least one functional element output in each preceding rank is provided to a data input of a plurality of functional elements in a succeeding logic rank.

2 more elements

A soft programmable logic array comprising:

a first logic rank of functional elements each of which produces logic functional outputs which are predetermined logic functions of the inputs,
a second rank of functional elements connected to said first rank each of which produces logic functional outputs which are predetermined logic functions of the inputs,
a third rank consisting of flip-flop pass-throughs connected to second rank to perform an inverting non-delayed pass-through or a latch function according to a predetermined function,
a fourth rank of functional elements connected to receive inputs from said third rank of flip-flop pass-throughs each of which produces logic functional outputs which are predetermined logic functions of the inputs,
a fifth rank consisting of flip-flop pass-throughs connected to said fourth rank to perform an inverting non-delayed pass-through or a latch function according to a predetermined function,
a sixth rank of functional elements connected to receive inputs from said fourth rank of flip-flop pass-throughs, each of which produces logic functional outputs which are predetermined logic functions of the inputs,
a seventh rank of flip-flop pass-throughs connected to receive data inputs from said said sixth rank to perform an inverting non-delayed pass-through or a latch function according to a predetermined function,
an output enable rank connected to receive inputs from said third, fifth and seventh ranks of flip-flop pass-through elements to provide data output for said logic array, and
control means connected to all of said functional elements and flip-flop pass-throughs for controlling and clocking said logic array and for providing latch inputs to set all of said functional elements and said flip-flop pass-throughs to perform a predetermined logic function, and
wherein the output of each functional element in each preceding logic rank is provided as one input to at least one functional element of a succeeding logic rank and at least one functional element output in each preceding rank is provided to a data input of a plurality of functional elements in a succeeding logic rank.

7 more elements

A soft programmable logic array comprised of:

a plurality of logic sectors, each sector having logic inputs and outputs which are independent from those of the other sectors of said plurality of logic sectors,
a plurality of logic ranks comprising each of said sectors, each logic rank formed of functional elements wherein each logic rank has its inputs connected to receive data input and produces data outputs which represent logic equations of the data inputs, where each functional element has a plurality of inputs connected to at least one output such that the output can be any logical function of the inputs, said functional elements including a plurality of latches equivalent to the number of possible output states for holding a logic indication of the associated outputs state corresponding to the logic function implemented, a plurality of ranks of flip-flop pass-throughs having inputs connected to receive outputs of one of said logic ranks and outputs connected to the inputs of another one of said logic ranks and to the output of said sector, each of which may invert a logic condition and pass that condition through without delay or latch a logic condition until released depending upon a predetermined logic function to be implemented, and
control means connected to all of the said sectors for setting all of said functional elements and all of said flip-flop pass-throughs to perform predetermined logic functions in each sector,
and wherein the output of each functional element in each preceding logic rank is provided as one input to at least one functional element of a succeeding logic rank and at least one functional element output in each preceding rank is provided to a data input of a plurality of functional elements in a succeeding logic rank.

1 more element

A soft programmable logic array for performing a preselected logic function on a data input function comprising:

a first rank of logic elements each of said logic elements consisting of functional elements having a plurality of data input receiving lines, at least one data output line and means for receiving and latching control signals representative of the function to be performed connected to receive data inputs to said system and a first set of logic signals to set the latches of said first rank of logic elements,
a second rank of logic elements connected to said first rank of logic elements, consisting of functional elements each having a plurality of data input receiving lines connected to said first rank, at least one data output line and means for receiving and latching control signals representative of the function to be performed connected to receive data inputs to said second rank and a second set of logic signals to set the latches of said second rank of logic elements,
a third rank of logic elements connected to said second rank and consisting of flip-flop pass-throughs having means for receiving and latching a third set of logic signals to control the function performed by said flip-flop pass-throughs,
a fourth rank of logic elements each of said logic elements consisting of functional elements each having a plurality of data input receiving lines, at least one data output line and means for receiving and latching control signals representative of the function to be performed connected to receive inputs from said third rank of flip-flop pass-throughs and having means for receiving and latching a fourth set of logic signals to set the latches of said functional elements to perform the predetermined logic function,
a fifth rank of logic elements connected to said fourth rank and consisting of flip-flop pass-throughs having means for receiving and latching a fifth set of logic signals to control the function performed by said flip-flop pass-throughs,
a sixth rank of logic elements consisting of functional elements connected to said fifth rank each having a plurality of data input receiving lines, at least one data output line and means for receiving and latching control signals representative of the function to be performed connected to receive data inputs from said fifth rank of flip-flop pass-throughs and having means for receiving a sixth set of logic signals to set the latches of said functional elements to perform the predetermined logic functions,
a seventh rank of logic elements connected to said sixth rank consisting of flip-flop pass-throughs each having a plurality of data input receiving lines, at least one data output line and means for receiving and latching control signals representative of the predetermined function to be performed, and
an output enable rank connected to receive inputs from said third, fifth, and seventh rank of flip-flop pass-through elements to provide data output for said logic array, and
wherein the output of each functional element in each preceding logic rank is provided as one input to at least one functional element of a succeeding logic rank and at least one functional element output in each preceding rank is provided to a data input of a plurality of functional elements in a succeeding logic rank.

6 more elements

In a single integrated circuit chip a programmable logic array (having at least data inputs to receive data from off-chip, configuration logical data inputs to receive configuration data which determines the logical equations which operate on the data from the data inputs, and data outputs) which can provide, on said data outputs, the solution to every possible logic equation applied to the data input to said logic array, and which can provide further logical operations on these solutions such that complex, multistep logic equations may operate on a given set of input data, and wherein said programmable logic array may be programmed and reprogrammed by configuration logical data (the logical or physical control of which may occur on- or off-chip) to provide during the normal operation of the system into which such array is incorporated a repeatable or changeable logical configuration to operate on any set of data input thereto wherein said array comprises:

at least two ranks of functional elements wherein
a first rank is comprised of configurable functional element means (hereinafter "FE"s) each FE having a plurality of data inputs (in this first rank, received from off-chip) having configuration logic inputs(s), and providing as output the solution to any logic equation which could be applied to the data input thereto, said FE being configurable by said configuration logic inputs, the ratio of the number of logical inputs to data inputs in each functional element being L/D such that the equation L=2.sup.D is satisified;
a second rank also comprised of FEs wherein the data outputs of each first rank FE provides data input to at least one of said second rank FEs and may provide one datum input to as many FEs as there are data inputs to each FE;
control means to direct the supply of configuration logic to input to each said FE, and wherein data outputs from each FE of lower numbered rank is provided to at least one FE data input of higher numbered rank and wherein data output from at least one FE of lower numbered rank provides data input to more than one FE data input of higher numbered rank.

1 more element

Dependencies are inferred from the claim text.

Description5,386 words

Summary823 words

#The present invention relates to a type of circuit known as a programmable logic array. Typically, programmable logic or very large scale integrated circuit (VLSI) circuit chips. These programmable logic array chips are of a type that when manufactured, the particular logic function of the circuit is not determined. A programmable logic array chip is designed so that the logic function of the chip may be subsequently determined. Most of such prior art chips are hard programmable in that they contain fuses or other elements which are permanantly burned or blown out in order to determine the logic function of the device. The present invention relates to a soft programmable device in that any particular device may be repeatedly programmed with the same or with different logic functions through a process of inputting logic functional data, which is sometimes known as characterization data. Although a soft programmable logic array requires the loading of characterization data in order to function, the logic array of the present invention is not merely a memory device. The characterization data is used to control the particular logic functions to be performed at particular logic levels in the array. In addition, chips according to the present invention are arranged with four quadrants or sectors and control circuitry on each chip so that several independent arrays are on one chip with common functional control.

#Known to applicant in the prior art is U.S. Pat. No. 3,818,252 which shows a plurality of word lines and digit lines as inputs to an array which contains fuses for the programmable elements. This patent shows, in effect, a variation of a standard programmable logic array having two levels for the production of a sum of products type of function, but does not anticipate the present multi-level soft programmable logic array. U.S. Pat. No. 4,233,667 also shows a programmable logic array, but which does not anticipate the present invention in structure or capability.

#U.S. Pat. No. 3,912,914 shows a programmable switching module which can become extremely complex for any particularly large switching function to be employed since the programming control for any switching function must be brought off the particular chip by individual wires to control the switching function. The present invention is programmed by inserting a stream of characterizing data which controls the various logic elements as a result of a characterizing process. Other patents known to applicant in the prior art are U.S. Pat. Nos. 3,855,536, 3,976,983 and 4,293,783, all of which show logic arrays but which either require programming control through external logic pins or which have limitations on the particular logic functions that may be accomplished.

Brief description of the drawings7 figures

#FIGS. 1A, 1B and 1C are intended to be viewed in left-to-right order, side-by-side, and represent a detailed logic diagram of one embodiment of the present invention.

#FIG. 2 is a detailed logic diagram of one of the functional elements according to the present invention and shown in FIGS. 1A, 1B and 1C.

#FIG. 3 is a detailed logic diagram of a pass-through/hold device according to the present invention and shown in FIGS. 1A, 1B and 1C.

Detailed description4,387 words

#FIGS. 1A, 1B and 1C contain, in left-to-right, side-by-side order, a detailed logic diagram of a soft programmable logic array 10 according to one embodiment of the present invention. The logical data inputs occur at the left-hand side of the diagram and progress through the various logic levels so that outputs, according to the predetermined programmed logic function, occur at the right-hand side of the diagram.

#A plurality of functional elements 12, 14, 16, 18, 20, 22, 24 and 26 make up the first logic level of the logic arra 10 according to the present invention. Functional elements 12 through 26 are all identical and the structure of functional element 12 is shown in detail in FIG. 2. Each functional element has three data inputs. The data inputs to functional element 12 are shown as A, B and C with number notation to show the particular functional element number. Similar notation is used for the data inputs for all eight functional elements of the first logic level. Each functional element, 12 through 26, has a single output which is interconnected with the remainder of the logic array 10, as shown in the diagram. A second level of logic is formed of six functional elements 28, 30, 32, 34, 36 and 38. The six functional elements, 28 through 38, are connected to six pass-through/hold devices 40, 42, 44, 46, 48 and 50. These pass-through/hold devices are all identical and a detailed diagram of a pass-through/hold device 40 is shown in FIG. 3. These six pass-through/hold devices constitute the third logic level of the present embodiment of the invention. The outputs of these six pass-through/hold devices are connected as shown in the diagram.

#The fourth level of logic in this embodiment of the present invention consists of four functional elements 52, 54, 56 and 58 which receive inputs as shown on the diagram. The outputs of these four functional elements of the fourth logic level are connected as inputs to four pass-through/hold devices which constitutes the fifth logic level. The pass-through/hold devices 60, 62, 64 and 66 constitute the fifth logic level. The sixth logic level consists of two functional elements 68 and 70. The outputs of functional elements 68 and 70 provide inputs to function/pass-through elements 72 and 74 which constitute the eighth logic level of this embodiment according to the present invention. In this figure, each functional element has a number with a prefix of FE with a particular element number. Similarly, all of the pass-through/hold devices are numbered with a particular number and the prefix FP.

Soft programmable logic array

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Soft programmable logic array

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Abstract

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Claims26

Description5,386 words

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Classification3 codes

Life of this patent

Description5,386 words