Parallel multiplier with a modified booth algorithm

A parallel multiplier circuit for forming a product of a binary multiplier value and a binary multiplicand value from a plurality of partial products determined from said binary multiplier and multiplicand values, each of said plurality of partial products corresponding to a different binary bit of said multiplier value such that each of said partial products has a relative significance reflecting the relative bit significance of the corresponding multiplier bit, said parallel multiplier circuit comprising:

• a plurality of rows of adder circuits arranged in an order of successively-increasing significance from a lowest-order adder row to a highest-order adder row,
• the adders in said lowest-order adder row receiving as inputs the two partial products with the lowest relative significance, and
• and the adders in each successively higher order row of adders receiving as inputs the one of the partial products with the next higher relative significance and an output from the adders in the next lower order row of adders,
• wherein each of said rows of adders includes at least one carry save adder, and
• wherein the number of said adders in each of said rows of adders increases from said lowest-order adder row to said highest-order adder row;
• negative product correcting means for supplying a first correction signal to the ones of said adder rows receiving negative partial-products signals, and for providing a second correction signal as an input to the adders in said lowest-order row of adders;
• and
• a final adder coupled to the outputs of said highest order row of adders to form said product.