Digital pipelined heterodyne circuit
AssigneeTektronix, Inc.
InventorYih-Chyun Jenq
Life of this patent
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Abstract
A digital pipelined heterodyne circuit includes sine and cosine function generators for generating m-bit digital coefficients and an m-stage digital multiplier for multiplying the coefficients by a digitized data input signal. A triangular shift register array connects the digital sine and cosine function generators with the multiplier stages and provides for simultaneous processing of successive bytes of input data at each multiplier stage by delaying the arrival of coefficient bits at each multiplier stage to coincide with the arrival of a predetermined data byte. This takes place simultaneously in all stages thereby decreasing the processing time by a factor of m.
Claims7
A digital heterodyne circuit comprising:
- (a) a data input line for receiving a sequence of digitized data signals;
- (b) digital sine and co-sine function generator means, each having m outputs for generating m-bit digital coefficients, one bit on each output, a predetermined time intervals as a function of time corresponding to sine .omega.t and co-sine .omega.t, respectively, where .omega. is a predetermined frequency;
- (c) m-stage arithmetic means for multiplying said data signals by said digital coefficients;
- and
- (d) delay means connecting said output of said function generator means for a corresponding stage of said arithmetic means for providing each respective bit of a digital coefficient to each such corresponding stage of said arithmetic means simultaneously with the arrival at each such corresponding stage of a predetermined one of said data signals.
A digital heterodyne circuit comprising:
- (a) a data input line for providing a digitized data input signal;
- (b) digital sine and cosine function generator means for generating m-bit digital coefficients at a predetermined frequency;
- (c) first arithmetic stage means for digitally multiplying the most significant bit of each m-bit coefficient, from said function generator means by a first data input signal, thereby producing a first product output;
- (d) second arithmetic stage means for digitally multiplying the next most significant bit of said m-bit coefficients from said function generator means by said first output product, thereby producing a second output product;
- (e) m.sup.th arithmetic stage means for multiplying the least significant bit of said m-bit coefficients from said function generator means by the (m-l)th output product, thereby producing a heterodyned data signal;
- and
- (f) triangular shift register means for providing each bit of said m-bit coefficients to each of said arithmetic stage means in timed relation such that said data input signal is processed sequentially by each of said arithmetic stage means simultaneously with the sequential processing of other data input signals.
Dependencies are inferred from the claim text.