Two-dimensional discrete cosine transform processor

A two-dimensional Discrete Cosine Transform (DCT) processor which uses a pair of one-dimensional DCT processors to produce the two-dimensional DCT of an N.times.N matrix of input data by a row-column decomposition method, comprising;

• a first N.times.1 DCT processor which computes the one-dimensional transform of said input data matrix, one column at a time, to yield a one-dimensional intermediate transform matrix,
• a N.times.N transposition memory for storing said intermediate trnsform matrix, and
• a second N.times.1 DCT processor which computes the one-dimensional transform of the transpose of the said intermediate transform matrix stored in said transposition memory to yield the desired two-dimensional DCT,
• wherein both of said N.times.1 DCT processors comprise;
• an N-stage input register to which a column of said matrix of input data or a row or column of said stored intermediate transform matrix is applied in bit-serial format,
• an N-stage holding register having its stages connected to the corresponding stages of said input register, and means to transfer the contents of said input register in bit-parallel format to said holding register each time the said input register fills up,
• distributed arithmetic circuitry connected to said holding register to concurrently compute N vector inner products, said distributed arithmetic circuitry comprising;
• first stage decimation in frequency circuitry connected to the output of said holding register, said decimation in frequency circuitry comprising means to produce a pair of N/2 bit words from each N bit word received from said holding register,
• said distributed arithmetic circuitry further comprising N RACs each comprising one or more ROMs plus an accumulator said RACs connected to the output of said decimation in frequency circuitry, and
• an N-stage output register having each of its stages connected to the corresponding accumulator of each of said RACs, said output register comprising means to receive said vector inner products from said accumulators in bit-parallel format and means to shift said inner products out in bit-serial format.

An N.times.1 Discrete Cosine Transform (DCT) processor comprising;

• an N-stage input register to which a column or row of input data may be applied in bit-serial format,
• an N-stage holding register having its stages connected to the corresponding stages of said input register, and means to transfer the contents of said input register in bit-parallel format to said holding register each time the said input register fills up,
• distributed arithmetic circuitry connected to said holding register to concurrently compute N vector inner products, said distributed arithmetic circuitry comprising;
• first stage decimation in frequency circuitry connected to the output of said holding register, said decimation in frequency circuitry comprising means to produce a pair of N/2 bit words from each N-bit word received from said holding register,
• said distributed arithmetic circuitry further comprising N RACs each comprising one or more read only memories (ROMs) plus an accumulator, said RACs being connected to the output of said decimation in frequency circuitry, and
• an output register having each of its stages connected to the corresponding accumulator of each of said RACs, said output register comprising means to receive said vector inner products from said accumulators in bit-parallel format and means to shift said inner products out in bit-serial format.

A two-dimensional Discrete Cosine Transfor:m (DCT) processor for producing the two-dimensional DCT transform of an N.times.N matrix of input data, comprising;

• first and second N.times.1 DCT processors and an N.times.N transposition memory,
• means to apply the transpose of said N.times.N matrix of input data to said first N.times.1 DCT processor to thereby compute an intermediate N.times.N matrix,
• means to store said intermediate matrix in said transposition memory, and,
• means to read out the transpose of said stored intermediate matrix to the input of said second N.times.1 DCT processor to thereby compute the two dimensional DCT of said matrix on input data,
• wherein each of said N.times.1 DCT processors comprises means to concurrently compute N vector inner products by means of circuitry which performs distributed arithmetic with first stage decimation in frequency and partial sums,
• and wherein said transposition memory comprises an N.times.N random access memory (RAM) array with separate read and write terminals and a read/write control circuit connected thereto and wherein the output of said first DCT processor is read in alternately row-wise and column-wise and the input of said second DCT processor is alternately read out from said memory row-wise and column-wise by said control circuit in such a way that the transposition of the stored matrix is achieved for application to said second N.times.1 DCT processor.