High performance signal processor

An array of processor chips interconnected to provide independent simultaneous operation for multiprocessing, comprising:

• at least first and second processor chips each including a plurality of input/output ports, each processor chip including an arithmetic section for processing data in accordance with a predetermined algorithm;
• memory means connected to said array for storage of data to be processed, said input/output ports being connected in parallel with said memory means;
• control means including address generator means on each of said processor chips for selecting data from said memory means for supply to the arithmetic section of the corresponding processor chip by way of said input/output ports, for processing said selected data, and for subsequent return of processed data to said memory means;
• and
• at least one of said chips being a redundant chip operating in parallel with another chip to provide a check on the processed data produced by at least one other of said chips.

A high performance, monolithic, autonomous signal processor chip for computing digital signal processing algorithms based on the Fast Fourier Transform, comprising:

• a multiplier array of bit-serial complex multipliers for carrying out four simultaneous bit-serial complex multiplications of four complex data words with four complex coefficients words, each multiplier including 20 bit slices to accommodate words up to 20 bits in length;
• an adder/subtractor matrix connected to said multiplier array to receive and combine output data from said bit serial complex multiplier array to produce high-precision serial result signals;
• result shift register means connected to said adder/substractor matrix for temporarily storing said result signals;
• input/output means connected to said multiplier array for supplying said selected data and coefficient words to said chip and connected to said result shift register means for transferring said result signals out of said chip;
• an address generation logic circuit for selecting from an external memory said data and coefficient words for multiplication by said multiplier array;
• a control sequencer connected to said multiplier array and to said address generation control logic for operating said multiplier array to perform said complex operations and to control all internal step-by-step operations needed for said chip to process data;
• and
• a mode controller connected to said control sequencer and to said address generation control logic circuit for selective operation of said chip, said mode controller being connectable to a chip external host computer, said mode controller activating said control sequencer to initiate a selected sequence of operations.

A processor chip array element, comprising:

• first and second high-performance, monolithic, autonomous signal processor chips for computing digital signal processing algorithms based on the Fast Fourier Transform, each of said processor chips including a multiplier array of bit-serial complex multipliers, an address generation control logic circuit for selecting data and coefficient words for multiplication by said multiplier array, a control sequencer for operating said multiplier array to perform complex multiplication, an adder/subtractor matrix connected to said multiplier to receive and combine outputs data from said bit-serial complex multiplier array to produce serial result signals, result shift register means for temporarily storing said result signals, input/output ports connected to said multiplier array and to said result shift register means, and a mode controller for selective operation and control interfacing with a chip external host computer via said input/output ports;
• clock generator means connected to synchronously drive said first and second processor chips;
• first and second memory means for said first and second processor chips, respectively;
• first address data bus means connecting the input/output ports of said first processor chip to said first memory means for storing first result signals from said first processor chip;
• second address and data bus means connecting the input/output ports of said second processor chip to said second memory means for storing second result signals from said second processor chip;
• and
• means connected to said first and second processors for comparing said first and second processor result signals, whereby one of said first and second processor chips serves as an active processor, and the other serves to check the accuracy of the active processor.