Logic gate system design

A method for designing a circuit system comprising a plurality of logic gates each having a gate input and a gate output with said circuit system having a plurality of system inputs and outputs, said logic gates to be electrically interconnected together at said gate inputs and outputs and to said system inputs and outputs in a selected manner, said method comprising:

• representing an initial design for said circuit system in a computer system which is capable of determining for this initial design so represented those logic values that will occur at said logic gate outputs in response to selected logic values being provided at said circuit system inputs in said initial design representation;
• providing a plurality of controllability count registers in said computer system for each of said gate inputs in said initial design representation with each such count register being capable of keeping a total of count increments provided thereto in said computer system, there being a said controllability count register in each said plurality of controllability count registers for each of those logic values which can occur at that said gate input corresponding thereto;
• providing a plurality of sensitivity count registers in said computer system for each pairing possible of said gate inputs and outputs in each of said logic gates in said initial design representation with each such count register being capable of keeping a total of count increments provided thereto in said computer system, there being a said sensitivity count register in each said plurality of sensitivity count registers for each gate input and output logic value pair which can occur at that gate input and output pair corresponding thereto;
• providing in sequence a plurality of sets of logic values in said computer system for said circuit system inputs in said initial design representation;
• determining in said computer system those logic values that will occur at said logic gate outputs in said initial design representation in response to each set of logic values provided at said circuit system inputs in said initial design representation, as aforesaid;
• incrementing each said controllability count register by one count if a logic value corresponding thereto appears at its corresponding gate input after each said determining of logic values;
• incrementing each sensitivity count register by one count if a pair of gate input and output logic values corresponding thereto appears at its corresponding gate input and output pair after each said determining of logic values, but only if gate input logic values occurring at those other said gate inputs of said corresponding logic gate are such that were a change to occur in that gate input logic value of such an appearing pair of gate input and output logic values that there would result a change in that gate output logic value of such appearing pair;
• and
• estimating what likelihoood exists in such initial design for detecting at some said circuit system output an incorrect logic value occurring at any logic gate input based on total counts occurring in each said controllability count register and in each said sensitivity count register after said plurality of sets of logic values has been provided for said circuit system inputs in said initial design representation, as aforesaid.