High-speed instruction control for vector processors with remapping

An instruction flow control system for a main processor for processing mapped and remapped instructions, mapped instructions being where the address or instructions is not loaded directly into an active control register but is modified prior to loading, remapped instructions being where the instruction is modified at least twice, said instructions including operation codes based on which the determination is made whether to remap said instructions, comprising:

• instruction buffer means connected to said main processor for receiving stored program instructions to be remapped;
• program address generator means connected to the instruction buffer means for fetching the program instructions to be remapped;
• map gate array means connected to said instruction buffer means for determining whether certain of said instructions from said instruction buffer are to be mapped or remapped and for instructions to be remapped generating an address including a constant address and a variable address which are indicative of a plurality of operation codes in response to a single remap program instruction being fetched from the instruction buffer means;
• and
• a program instruction translate RAM connected to the output of said map gate array means for decoding each of said constant and said variable address into a plurality of operation code instructions for controlling said main processor, whereby a plurality of operation codes may be generated from a single instruction to be remapped by said map gate array means and said program instruction translate ram.