US 4,791,557 AGranted

Apparatus and method for monitoring and controlling the prefetching of instructions by an information processing system

AssigneeWang Laboratories, Inc.

InventorsDavid J. Angel, Gary A. Cardone, Mark D. Holbrook, James P. Moskun, Bruce Patterson

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Abstract

An information processing system includes a processor responsive to instructions for performing operations. The processor includes instruction queue for fetching and storing instructions in advance of execution and the system is responsive to certain of the instructions for causing execution of a corresponding sequence of instructions. A prefetch monitor includes circuitry for detecting instructions which may result in the execution of a corresponding sequence of instructions. The prefetch monitor further includes an instruction substitution circuit which is responsive to the detecting circuitry for inhibiting the reading of following instructions from a memory to the processor and is responsive to instruction fetching operation of the processor for reading null instructions to the processor. The prefetch monitor also includes a synchronization which is responsive to a fetching operation of the processor circuit for detecting transfer of execution to a next valid instruction, wherein the substitution circuit is responsive to the synchronization circuit for resuming reading of instructions from the memory to the processor with the next valid instruction. The synchronization includes circuitry for maintaining synchronization between the operations of substituting null instructions and the execution of the instructions. In a specific implementation, the instructions which may result in the execution of a corresponding sequence of instructions are foreign to the system, a corresponding non-maskable interrupt results in the execution of a routine which emulates the execution of the foreign instruction and the null instructions are jump-to-self instructions.

Claims22

Dependent claims

In an information processing system including memory means for storing instructions, processor means responsive to the instructions for performing operations, the processor means including instruction queue means for fetching and storing instructions in advance of execution, the instruction queue means fetching instructions over a system data bus from locations in the memory means in response to substantially sequential addresses generated by an instruction pointer register means, the addresses being issued over an address bus to the memory means, and means responsive to certain of the instructions fetched by the instruction queue means for causing execution of an alternate sequence of instructions, prefetch monitor means, comprising:

means, coupled to the system data bus, for detecting instructions fetched by the instruction queue means which may result in the execution of an alternate sequence of instructions;
means for inhibiting the fetching of a next instruction from the memory means to the processor means, the inhibiting means being coupled to the detecting means and responsive to the operation thereof for inhibiting the fetching of the next instruction when the detecting means detects an instruction which may result in the execution of an alternate sequence of instructions;
and
means, coupled to the system data bus and to the detecting means and responsive to the instruction queue fetching operation of the processor means, for substituting null instructions upon the system data bus for storage within the instruction queue means, each of the null instructions being a type of instruction the execution of which prevents the instruction pointer register means from incrementing such that at the completion of the execution of the alternate sequence of instructions and also the null instructions stored within the instruction queue means the address within the instruction pointer register means points to the location in the memory means of the next instruction following the instruction which resulted in the execution of the alternate sequence of instructions.

1 more element

In an information processing system including memory means for storing instructions, processor means responsive to the instructions for performing operations, the processor means including instruction queue means for fetching and storing instructions in advance of execution, the instruction queue means fetching instructions over a system data bus from locations in the memory means in response to substantially sequential addresses generated by an instruction pointer register means, the addresses being issued over ann address bus to the memory means, and means responsive to certain of the instructions fetched by the instruction queue means for causing execution of an alternate sequence of instructions, a method for preventing a loss of system state resulting from the execution of such certain instructions, comprising the steps of:

detecting instructions, fetched by the instruction queue means over the system data bus, which may result in the execution of an alternate sequence of instructions:
responsive to the step of detecting an instruction which may result in the execution of an alternate sequence of instructions,
inhibiting the fetching of a next instruction from the memory means to the processor means, and
responsive to the instruction queue fetching operation of the processor means
substituting null instructions upon the system data bus for storage within the instruction queue means, each of the null instructions being a type of instruction the execution of which prevents the instruction pointer register means from incrementing such that at the completion of the execution of the alternate sequence of instructions and also the null instructions stored within the instruction queue means the address within the instruction pointer register means points to the location in the memory means of the next instruction following the instruction which resulted in the execution of the alternate sequence of instructions.

2 more elements

Dependencies are inferred from the claim text.