Apparatus and method for addressing semiconductor arrays in a main memory unit on consecutive system clock cycles

An apparatus for addressing memory locations in response to address signals which are maintained on a bus for a limited time, said apparatus comprising:

• a memory unit;
• first means, coupled between said bus and said memory unit, for generating an enable signal during said limited time upon receipt of an address signal from said bus or said memory unit and for maintaining said enable signal beyond said limited time to permit said memory unit to respond to said address signal, said first means including
• a first latch being responsive to said receipt of said address signal to generate a first latch signal lasting for a first period of time, said first latch signal providing at least a first portion of said enable signal and being sufficiently fast to maintain at least some overlap of said first portion with any earlier portion of said enable signal, and
• a second latch being responsive to said first latch signal to generate a second latch signal lasting for a second period of time, said second latch signal providing at least a second portion of said enable signal and being sufficiently fast to maintain at least some overlap with said first portion of said enable signal and being of sufficient duration to assure that said enable signal extends beyond said limited time;
• and
• second means, having an enable signal input terminal coupled to receive said enable signal from said first means and being coupled between said bus and said memory unit, for receiving and supplying said address signal to said memory unit in response to said receipt of said enable signal and for maintaining said address signal for said memory unit for the duration of said enable signal,
• whereby said address signal is available to said memory unit for a sufficiently long time period to permit operation of said memory unit without maintaining said address signal on said bus for the entire long time period needed for operation of said memory unit.