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US 4,791,551 AGranted
Microprogrammable devices using transparent latch
AssigneeAnalog Devices, Inc.
InventorDouglas Garde
Life of this patent
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AssigneeAnalog Devices, Inc.
InventorDouglas Garde
Estimating the term…
In a microprogammed controller, the conventional pipeline register is replaced by a pair of coupled latches: a so-called "transparent" latch is placed between the output of the microprogram memory and the input of one or more system resources including at least the sequencer or address generator, and another latch is placed between the output of each such resource and the destination of its output. The appropriate bits of a microinstruction are supplied from the microinstruction memory to the associated resource via the transparent latch. The clock signal for the sequencer or other resource serves as the enable signal for the output latch (which can be either a transparent latch or an edge-triggered latch resposive to the rising edge of the clock signal), while the inverted sense of the clock signal provides the enable signal for the transparent latch. This allows data to propagate through the resource to internal destinations therein even before the results of the previous instruction are cleared from the resource's output latch. Set-up conditions for an instruction thus can occur within a resource while the results of the previious instruction are still sitting in the resource's output latch. Therefore those set-up conditions can already have been completed (or at least partially completed) before the results of the prior instruction are cleared out of the output latch and the new microinstruction is latched into the input latch.
Apparatus for use in a programmed control unit for receiving and processing instructions from an instruction memory, comprising, in combination:
In an information processing system for executing microinstructions, said system including a microinstruction memory, a system resource having input terminals and output terminals, means for providing to the microinstruction memory successive addresses of microinstructions to be fetched, and the microinstruction memory providing at its outputs microinstructions in response to addresses supplied to its address inputs, the improvement comprising:
A digital information processing system for executing digital instructions, any two successive instructions being termed first and second instructions, respectively, the system comprising:
In a digital information processing system for executing microinstructions and having a microinstruction memory, a microprogram sequencer and at least one system resource for receiving and acting upon various bit fields of the microinstructions, the improvement comprising:
In an information processing system for executing microinstructions, said system including a microinstruction memory, a sequencer for providing to the microinstruction memory successive addresses of microinstructions to be fetched, and the microinstruction memory providing at its outputs microinstructions in response to addresses applied to its address inputs, the improvement comprising:
In an information processing system for executing microinstructions, said system including a microinstruction memory, a sequencer for providing to the microinstruction memory successive addresses of microinstructions to be fetched, and the microinstruction memory providing at its output microinstructions in repsonse to addresses supplied to its address inputs, the improvement comprising;
In an information processing system for executing microinstructions, said system including a microinstruction memory, an address generator, a data memory addressable by the address generator, means for providing to the microinstruction memory successive addresses of microinstructions to be fetched, and the microinstruction memory providing at its outputs microinstructions in response to addresses supplied to its address inputs, the improvement comprising:
A method of operating an instruction sequencer used to generate successive addresses of instructions to be fetched from an instruction memory in an information processing system controlled by a clocking signal which alternates between first and second states, comprising, for each instruction the steps of:
Dependencies are inferred from the claim text.