US 4,791,488 A · Line-locked clock signal generation system

Abstract

A television receiver includes a phase-locked loop (PLL) which generates a clock signal having a frequency of N times the line frequency and being phase-locked to the horizontal line synchronizing signal. The clock signal produced by this PLL has a frequency which tends to jitter between N+1 and N-1 times the line frequency. To compensate for this jittering in the frequency of the clock signal, phase alignment circuitry is coupled to the PLL to align the phase of the clock signal to the horizontal drive signal produced by the PLL on the occurrence of each horizontal drive pulse. The PLL also includes a delay element which delays the horizontal drive signal applied to the phase comparator of the PLL. This delay element effectively advances the phase of the horizontal drive signal and the line-locked clock signal with respect to the horizontal sync signal to compensate for signal processing delays imparted in the generation of the horizontal drive signal and the clock signal.

Claims7

Dependent claims

A clock signal generation system comprising:

a source of reference signal having a frequency that is substantially equal to a predetermined frequency;
a phase locked loop, coupled to said source of reference signal for generating first and second oscillatory signals that are locked in phase to said reference signal, wherein said first oscillatory signal has a nominal frequency of N times said predetermined frequency, N being an integer greater than 1, and is subject to undesirable variations in frequency between predetermined minimum and maximum values, and said second oscillatory signal has a frequency substantially equal to said predetermined frequency;
and
signal phase alignment means, coupled to said phase locked loop for compensating for the undesirable variations in frequency of said first oscillatory signal, including:
means, responsive to said first oscillatory signal for developing M further oscillatory signals representing M respectively different phases of said first oscillatory signal where M is an integer greater than 1;
and
means responsive to said second oscillatory signal for continually selecting from among said M further oscillatory signals, an output oscillatory signal having a transition which is approximately coincident with a transition in said second oscillatory signal.

4 more elements

A digital television signal processing system comprising:

a source of television signal including a horizontal line synchronizing signal component having a frequency substantially equal to a predetermined frequency;
television signal processing means coupled to said source including means for separating the horizontal line synchronizing signal from said television signal;
a phase locked loop, coupled to said television signal processing means for generating first and second oscillatory signals that are locked in phase to said separated horizontal line synchronizing signal, wherein, said first oscillatory signal has a nominal frequency of N times said predetermined frequency, N being an integer greater than 1, and is subject to undesirable variations in frequency between predetermined minimum and maximum values, and said second oscillatory signal has a frequency substantially equal to said predetermined frequency;
and
signal phase alignment means, coupled to said phase locked loop for developing a clock signal from said first oscillatory signal, said clock signal being compensated for the undesirable variations in the frequency of said first oscillatory signal, said signal phase alignment means comprising:
means, responsive to said first oscillatory signal for developing M further oscillatory signals representing M respectively different phases of said first oscillatory signal, where M is an integer greater than 1;
and
means, responsive to said second oscillatory signal for continually selecting from among said M further oscillatory signals, a signal to be provided as said clock signal, wherein a transition in said selected further oscillatory signal is substantially coincident with a transition in said second oscillatory signal.

5 more elements

Dependencies are inferred from the claim text.

Line-locked clock signal generation system

Life of this patent

Line-locked clock signal generation system

Life of this patent

Abstract

Claims7