Predictive time base control circuit for a waveform system

A time base control circuit for a waveform sampling system of the type which samples an input waveform, converts a waveform sample into representative digital data, and stores the representative digital data in an addressable memory, wherein timing of waveform sampling is controlled by a periodic sampling control signal, the time base control circuit comprising:

• a trigger generator for generating a triggering signal in response to a triggering event in the input waveform to be sampled;
• a triggered oscillator responsive to said triggering signal for generating a first periodic clock signal of constant frequency commencing upon generation of said triggering signal;
• and
• means responsive to said first periodic clock signal for generating said periodic sampling control signal, said periodic sampling control signal being delayed from said first periodic clock signal by an adjustable delay time wherein said means for generating said periodic sampling control signal comprises:
• a skewing circuit responsive to said first periodic clock signal for generating a second periodic clock signal having a frequency equal to that of said first periodic clock signal, said second periodic clock signal being phase skewed from said first periodic clock signal by an adjustable phase angle;
• a timing circuit responsive to said first periodic clock signal and said triggering signal for generating an enabling signal after an adjustable time interval, said timing circuit measuring said time interval by counting periods of said first periodic clock signal following said triggering signal;
• a first frequency divider responsive to said enabling signal for dividing said second periodic clock signal frequency by a predetermined amount following generation of said enabling signal thereby to produce a third periodic clock signal;
• and
• logic gate means for combining said second and third periodic clock signals to form said periodic sampling control signal.

A time base control circuit for a waveform sampling system of the type which samples an input waveform, converts a waveform sample into representative digital data, and stores the representative digital data in an addressable memory, wherein timing of waveform sampling is controlled by a periodic sampling control signal and wherein timing of storage of said representative digital data is controlled by a write control signal applied to said memory, the time base control circuit comprising:

• a trigger generator for generating a triggering signal in response to a triggering event in the input waveform to be sampled;
• a triggered oscillator responsive to said triggering signal for generating a first periodic clock signal of constant frequency commencing upon generation of said triggering signal;
• means responsive to said first periodic clock signal for generating said periodic sampling control signal, said periodic sampling control signal being delayed from said first periodic clock signal by an adjustable delay time:
• first means for producing a periodic write control signal in delayed response to said periodic sampling control signal, said periodic write control signal being applied to said addressable memory for controlling timing of storage by said addressable memory of digital data representative of waveform samples produced by said waveform sampling system in response to said periodic sampling control signal;
• and
• memory addressing means responsive to said periodic write control signal for providing address data for addressing said addressable memory, said address data being incremented by an incrementing amount in response to each period of said periodic write control signal wherein said means for generating said periodic sampling control signal comprises:
• a skewing circuit responsive to said first periodic clock signal for generating a second periodic clock signal having a frequency equal to that of said first periodic clock signal, said second periodic clock signal being phase skewed from said first periodic clock signal by an adjustable phase angle;
• a timing circuit responsive to said first periodic clock signal and said triggering signal for generating an enabling signal after an adjustable time interval, said timing circuit measuring said time interval by counting periods of said first periodic clock signal following said triggering signal;
• a first frequency divider responsive to said enabling signal for dividing said second periodic clock signal frequency by a predetermined amount following generation of said enabling signal thereby to produce a third periodic clock signal;
• and
• logic gate means for combining said second and third periodic clock signals to form said periodic sampling control signal.

A method for controlling the timing of waveform sampling by a waveform sampling system of the type which samples an input waveform, converts a waveform sample into representative digital data, and stores the representative digital data in an addressable memory, the method comprising the steps of:

• generating a triggering signal in response to a triggering event in the input waveform to be sampled;
• generating a first periodic clock signal of constant frequency commencing upon generation of said triggering signal;
• and
• generating a periodic sampling control signal in response to said first periodic clock signal, said periodic sampling control signal being delayed from said first periodic clock signal by an adjustable delay time and applied to said waveform sampling system for periodically initiating waveform sampling wherein the step of generating said periodic sampling control signal comprises the steps of:
• generating a second periodic clock signal having a frequency equal to that of said first periodic clock signal, said second periodic clock signal being phase skewed from said first periodic clock signal by an adjustable phase angle;
• generating an enabling signal after an adjustable time interval, said time interval being determined by counting periods of said first periodic clock signal following said triggering signal;
• generating a third periodic clock signal following generation of said enabling signal by frequency dividing said second periodic clock signal;
• and
• combining said second and third periodic clock signals to form said periodic sampling control signal.