US 4,791,358 A · Integrated circuits, carriers therefor and testing apparatus and method for the foregoing

Abstract

A method of testing an interconnection function between two integrated circuits which are mounted on a carrier and which are interconnected by data connections, for example a printed wiring board, is disclosed. The integrated circuits are also connected to a serial bus via which test patterns and result patterns can be communicated between a test device which can be connected thereto and the respective integrated circuits. The bus of a preferred embodiment is formed by a so-called I.sup.2 C bus. In a further elaboration, this set-up can also be used for testing the internal logic circuitry of the integrated circuits. For the testing of the interconnection function, input/output cells with a parallel connection for performing the normal execution function in a transparent mode are provided. They also include series connections for communication test/result patterns by way of a shift register.

Claims4

Dependent claims

A method of testing a carrier provided with a plurality of interconnected integrated circuits, said method comprising the steps of:

providing said integrated circuits with test bit string inputs and result bit string outputs;
interconnecting said inputs and outputs by means of a serial bus that includes at least one clock line and at least one data line;
selecting at least one first of said integrated circuits in a test input state for receiving a lost bit string via said bus;
setting at least said first integrated circuit and at least one second of said integrated circuits to an execution state while activating an interconnection function between said first and second integrated circuits and forming a result pattern on the basis of the test bit string;
selecting at least one said second integrated circuit for, in a test output state, outputting a result bit string via said bus;
and
characterizing said carrier with respect to a correct/incorrect operation of said integrated circuits cum interconnection function.

4 more elements

Dependencies are inferred from the claim text.

Integrated circuits, carriers therefor and testing apparatus and method for the foregoing

Life of this patent

Integrated circuits, carriers therefor and testing apparatus and method for the foregoing

Life of this patent

Abstract

Claims4