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US 4,791,320 AGranted
Bipolar-MISFET compound inverter with discharge transistor
AssigneeFujitsu Limited
InventorsMitsuya Kawata, Tetsu Tanizawa
Life of this patent
Estimating the term…
Abstract
A compound transistor type inverter, i.e., comprised of MIS and bipolar transistors, including, at the output stage thereof, an npn transistor operative to charge a load. The npn transistor can be quickly cut OFF by an additional transistor, and simultaneously, the additional transistor is operative to attain a quick discharge from the load. Still another additional transistor is employed, in a case where the inverter includes a pnp transistor, other than the npn transistor, at a ground side, which another additional transistor is operative to bypass the collector and emitter of the pnp transistor.
Claims9
A compound transistor type inverter comprising:
- an input stage MIS transistor pair comprising p-channel MIS transistor and an n-channel MIS transistor both being connected in series betwen a power source and a ground and connected commonly, at their gates, with an input terminal;
- an output stage transistor pair comprising an npn transistor and an n-channel MIS transistor being provided with a common output terminal connected to a series connection node between the npn transistor and the n-channel MIS transistor, said transistors being connected in series between the power source and the ground, the n-channel MIS transistor being connected, at the gate thereof, to the input terminal of the npn transistor being controlled, via the base thereof, by an output from the input stage MIS transistor pair;
- and
- an additional transistor means connected in the inverter, which additional transistor means is operative to shunt current between the base and the emitter of the npn transistor so as to attain a quick cut off of the npn transistor and, at the same time, attain a quick discharge of current to be drawn from the output terminal to the ground via the n-channel MIS transistor at the input stage.
1 more element
A compound transistor type inverter comprising:
- an input stage MIS transistor pair comprising a p-channel MIS transistor and n-channel MIS transistor both being connected in series between a power source and a ground and connected commonly, at their gates, with an input terminal;
- an output stage transistor pair comprising an npn transistor and a pnp transistor being provided with a common output terminal connected to a series connection between the npn and the pnp transistors, said output transistors being connected in series between the power source and the ground, the npn and pnp transistors being commonly controlled, via their bases, by an output from the input stage MIS transistor pair;
- and
- an additional transistor means connected in the inverter, which additional transistor means is connected to said input terminal and controlled thereby to turn on when said npn transistor turns on and to turn off when said npn transistor turns off, and is operative when turned on to shunt current between the base and the emitter of the npn transistor so as to attain a quick cut-OFF of the npn transistor and, at the same time, attain a quick discharge of current to be drawn from the output terminal to the ground via the n-channel MIS transistor at the input stage.
1 more element
A compound transistor type inverter comprising:
- an input stage MIS transistor pair comprising a p-channel MIS transistor and n-channel MIS transistor both being connected in series between a power source and a ground and connected commonly, at their gates, with an input terminal;
- an output stage transistor pair comprising an npn transistor and a pnp transistor being provided with a common output terminal connected to a series connection between the npn and the pnp transistors, said output transistors being connected in series between the power source and the ground, the npn and pnp transistors being commonly controlled, via their bases, by an output from the input stage MIS transistor pair;
- an additional transistor means connected in the inverter, which additional transistor means is operative to shunt current between the base and the emitter of the npn transistor so as to attain a quick cut-OFF of the npn transistor and, at the same time, attain a quick discharge of current to be drawn from the output terminal to the ground via the n-channel MIS transistor at the input stage;
- and
- another additional transistor means connected in the inverter so as to be operative to bypass the emitter and collector of said pnp transistor.
2 more elements
A compound transistor type inverter comprising:
- an input stage MIS transistor pair comprising a p-channel MIS transistor and n-channel MIS transistor both being connected in series between a power source and a ground and connected commonly, at their gates, with an input terminal;
- an output stage transistor pair comprising an npn transistor and a pnp transistor being provided with a common output terminal connected to a series connection between the npn and the pnp transistors, said output transistors being connected in series between the power source and the ground, the npn and pnp transistors being commonly controlled, via their bases, by an output from the input stage MIS transistor pair;
- An additional transistor means connected in the inverter, which additional transistor means is operative between the base and the emitter of the npn transistor so as to attain a quick cut-OFF of the npn transistor and, at the same time, attain a quick discharge of current to be drawn from the output terminal to the ground via the n-channel MIS transistor at the input stage, and
- said additional transistor means comprises an n-channel MIS transistor having a gate connected to said input terminal.
1 more element
A bipolar-MISFET inverter comprising:
- an input terminal (11);
- an output terminal (16);
- a first power source (Vcc);
- a second power source (GND) supplying a voltage lower than that of the first power source;
- a p-channel MIS transistor (12), the source and the gate thereof being connected, respectively, to the first power source and the input terminal;
- a first n-channel MIS transistor (13), the source, the gate and the drain thereof being connected, respectively, to the second power source, the input and the drain of said p-channel MIS transistor (12);
- an npn transistor (14), the collector, the base and the emitter thereof being connected, respectively, to the first power source, the drain of said p-channel MIS transistor (12) and the output terminal;
- a second n-channel MIS transistor (15), the drain, the gate and the source thereof being connected, respectively, to the output terminal, the input terminal and the second power source;
- and
- a third n-channel MIS transistor (31) coupled between the output terminal and the drain of the first n-channel MIS transistor (13), the gate thereof being connected to the input terminal.
7 more elements
A bipolar-MISFET inverter comprising:
- an input terminal (11);
- an output terminal (16);
- a first power source (Vcc);
- a second power source (GND) supplying a voltage lower than that of the first power source;
- a p-channel MIS transistor (12), the source and the gate thereof being connected, respectively, to the first power source and the input terminal;
- a first n-channel MIS transistor (13), the source, the gate and the drain thereof being connected, respectively, to the second power source, the input and the drain of said p-channel MIS transistor (12);
- an npn transistor (14), the collector, the base and the emitter thereof being connected, respectively, to the first power source, the drain of said p-channel MIS transistor (12) and the output terminal;
- a pnp transistor (25), the collector, the base and the emitter thereof being connected, respectively, to the second power source, the drain of said p-channel MIS transistor (12) and the output terminal;
- and
- a second n-channel MIS transistor (31) coupled between the output terminal and the drain of the first n-channel IS transistor (13), the gate thereof being connected to the input terminal.
7 more elements
Dependencies are inferred from the claim text.