Center frequency high resolution digital phase-lock loop circuit

A center frequency high resolution digital phase-lock loop circuit comprising:

• digital phase correction means, having coupled thereto an input clock reference signal with a frequency f, and coupled therefrom a clock output phase-locked frequency, where f, is centered at said output phase locked frequency;
• divided-by-K circuit means for dividing said clock output phase-locked frequency by an integer K, to derive a data receive clock phase-locked to incoming data transitions;
• phase detector means having said data receive clock and said incoming data coupled thereto for generating phase correction signals whenever said data receive clock does not coincide in time with said incoming data transitions, and for coupling said phase correction signals to said digital phase correction means to selectively introduce a fixed delay in said clock output phase locked frequency, such that said clock output phase locked frequency equals said clock reference signal frequency;
• said phase detector means including means for generating phase correction signals which are either phase advance or phase retard signals respectively, when said data receive clock is either late or early, respectively, with respect to said incoming data transitions;
• wherein said digital phase correction means includes means for resetting said phase advance or phase retard signals after the phase of said clock output signal is corrected and a digital delay line means for providing an incremental delay from 0 to 360 degrees of the period of said clock reference signal;
• and
• shift register means for selecting a desired incremental delay from said delay line;
• and
• clock correction control means for controlling said shift register means in accordance with said phase advance and phase retard signals to select said incremental delay from said delay line.