High-speed multiplexer circuit

#Related subject matter is disclosed in the following application filed concurrently herewith and assigned to the same Assignee hereof: U.S. patent application Ser. No. 109,009 entitled "A High-Speed Demultiplexer Circuit", inventor R. G. Swartz.

#This invention relates to high-speed digital circuits and more particularly to high-speed digital multiplexer circuits.

#To exploit the high data transmission rate of optical fibers, new circuit technologies and architectures are evolving. Digital communication systems which operate at these higher data rates require multiplexers (MUX) and demultiplexers (DEMUX) which operate in the several giga-bits-per-second (Gb/s) range. To achieve the optimum data speed, circuits must operate at the maximum NRZ (non-return-to-zero) data rate possible for the particular technology.

#In the drawing,

#FIG. 1 shows a symbolic latch useful in understanding basic latch operations;

#FIG. 2 shows a multiplexer latch (M-latch) which is one of the building blocks used in the present invention;

#Analogous elements occurring in different figures are generally identified by the same reference designation. An element reference designation beginning with a number indicates the figure in which that element is first illustrated (e.g., 4A1 is shown in FIG. 4).

#In accordance with the present invention, a MUX architecture is disclosed that operates at the highest data rate possible while satisfying several design constraints. These design constraints may be summarized as follows: Circuits must operate at the maximum NRZ data rate possible within the limits of a particular technology. This data rate is defined to be 1/Td, where Td is the time delay of a single gate under appropriate loading conditions (typically with a fanout of 3 to 4). For example, a technology with a loaded gate delay of 100 ps (pico seconds) is required to be internally capable of NRZ operation at 10 Gb/s. Circuits must function without the need for multiple adjustable delay lines. No more than one variable delay line is permitted (one delay line is used to synchronize the external clock and data). The MUX must be able to handle multiple channel input data arriving simultaneously at the data inputs. This requirement implies that staggering of input data is not permitted for the MUX.

#The above requirements provide maximum benefit in communication system applications, where the highest operating speed possible is of paramount concern, and yet numerous user manual adjustments must be avoided because of expense and reliability issues.