US 4,789,963 AGranted

Display control apparatus for controlling to write image data to a plurality of memory planes

AssigneeFujitsu Limited

InventorsHitoshi Takahashi, Kiminori Fujisaku

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Abstract

A method for controlling a plurality of memory planes in a writing operation in a display control apparatus of a graphic system, the method including the steps of selectively connecting a plurality of the memory planes to a data bus by using an interface unit; selectively applying a write enable signal to the memory planes from a plane designating unit; applying data to be written to the data bus from a central processing unit; writing the data into the memory planes to which the write enable signal has been applied and which are connected to the data bus; and writing predetermined fixed data into the memory planes to which is the write enable signal has been applied but which are not connected to the data bus.

Claims9

Dependent claims

An apparatus for controlling a plurality of memory planes during a writing operation for a display control apparatus of a graphic system having a common data bus carrying data from a central processing unit producing a write designating signal and a plane designating signal, said apparatus comprising:

a plurality of memory planes for storing color image data using a single address signal transmitted from the central processing unit;
a plurality of plane designating units, corresponding and connected to said memory planes, for selectively applying a write enable signal to all said memory planes in dependence on the write designating signal and the plane designating signal, each plane designating unit comprising gate means for receiving the plane designating signal and the write designating signal and when both the plane designating signal and the write designating signal are received said gate means outputs the write enable signal;
a plurality of interface units, corresponding and connected to said memory planes and the common data bus, for selectively connecting said memory planes to the common data bus to write said color image data therein;
a plurality of interface control units, corresponding and connected to said interface units, for controlling the turning on or off of the corresponding interface units;
predetermined data means, connected to at least one memory plane disconnected from said common data bus, for applying, to the at least one memory plane disconnected from said common data bus, predetermined data which is inverted compared to said color image data written into said memory plane connected to said common data bus;
and
the at least one memory plane connected to said common data bus and the at least one memory plane disconnected from said common data bus being set to a write enable state by the write enable signal transmitted from a corresponding plane designating unit and when said color image data from said common data bus is written into the at least one connected memory plane, the at least one memory plane disconnected from said common data bus having written therein simultaneously the predetermined data transmitted from said predetermined data means.

4 more elements

a plurality of memory planes for storing color image data using a single address signal transmitted from the central processing unit;
a plurality of plane designating units, corresponding and connected to said memory planes, for selectively applying a write enable signal to all said memory planes in dependence on the write designating signal and the plane designating signal;
a plurality of interface units, corresponding and connected to said memory planes and the common data bus, for selectively connecting said memory planes to the common data bus to write said color image data therein:
a plurality of interface control units, corresponding and connected to said interface units, for controlling the turning on or off of the corresponding interface units;
predetermined data means, connected to at least one memory plane disconnected from said common data bus, for applying, to the at least one memory plane disconnected from said common data bus, predetermined data which is inverted compared to said color image data written into said memory plane connected to said common data bus;
and
the at least one memory plane connected to said common data bus and the at least one memory plane disconnected from said common data bus being set to a write enable state by the write enable signal transmitted from a corresponding plane designating unit and when said color image data from said common data bus is written into the at least one connected memory plane, the at least one memory plane disconnected from said common data bus having written therein simultaneously the predetermined data transmitted from said predetermined data means;
and
said plane designating units each comprising:
a plane designating flip-flop circuit, connected to the common data bus, for storing the plane designating signal;
and
an AND gate circuit, connected to said flip-flop and the corresponding memory plane, for generating said write enable signal.

9 more elements

a plurality of memory planes for storing color image data using a single address signal transmitted from the central processing unit;
a plurality of plane designating units, corresponding and connected to said memory planes, for selectively applying a write enable signal to all said memory planes in dependence on the write designating signal and the plane designating signal;
a plurality of interface units, corresponding and connected to said memory planes and the common data bus, for selectively connecting said memory planes to the common data bus to write said color image data therein;
a plurality of interface control units, corresponding and connected to said interface units, for controlling the turning on or off of the corresponding interface units;
predetermined data means, connected to at least one memory plane disconnected from said common data bus, for applying, to the at least one memory plane disconnected from said common data bus, predetermined data which is inverted compared to said color image data written into said memory plane connected to said common data bus;
and
the at least one memory plane connected to said common data bus and the at least one memory plane disconnected from said common data bus being set to a write enable state by the write enable signal transmitted from a corresponding plane designating unit and when said color image data from said common data bus is written into the at least one connected memory plane, the at least one memory plane disconnected from said common data bus having written therein simultaneously the predetermined data transmitted from said predetermined data means;
and
said interface control units each comprising a flip-flop circuit, connected to the common data bus the corresponding interface unit, for storing an interface control signal for controlling the turning on or off of the corresponding interface unit.

6 more elements

Dependencies are inferred from the claim text.

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Abstract

a plurality of memory planes for storing color image data using a single address signal transmitted from the central processing unit;
a plurality of plane designating units, corresponding and connected to said memory planes, for selectively applying a write enable signal to all said memory planes in dependence on the write designating signal and the plane designating signal, each plane designating unit comprising gate means for receiving the plane designating signal and the write designating signal and when both the plane designating signal and the write designating signal are received said gate means outputs the write enable signal;
a plurality of interface units, corresponding and connected to said memory planes and the common data bus, for selectively connecting said memory planes to the common data bus to write said color image data therein;
a plurality of interface control units, corresponding and connected to said interface units, for controlling the turning on or off of the corresponding interface units;
predetermined data means, connected to at least one memory plane disconnected from said common data bus, for applying, to the at least one memory plane disconnected from said common data bus, predetermined data which is inverted compared to said color image data written into said memory plane connected to said common data bus;
and
the at least one memory plane connected to said common data bus and the at least one memory plane disconnected from said common data bus being set to a write enable state by the write enable signal transmitted from a corresponding plane designating unit and when said color image data from said common data bus is written into the at least one connected memory plane, the at least one memory plane disconnected from said common data bus having written therein simultaneously the predetermined data transmitted from said predetermined data means.

4 more elements