Carry-look-ahead adder including bipolar and MOS transistors

An arithmetic operation circuit comprising:

• (i) first means for outputting an AND signal of corresponding bits of the plurality of digital signals to be subjected to an arithmetic operation;
• (ii) second means for outputting an exclusive OR signal of corresponding bits of the plurality of digital signals to be subjected to an arithmetic operation;
• and
• (iii) a carry propagation circuit including:
• (a) an output node,
• (b) first and second potential nodes,
• (c) a bipolar transistor having its collector-emitter path connected between said output node and said first potential node,
• (d) a first impedance element connected between said second potential node and a base electrode of said bipolar transistor, for forming a current path between said second potential node and said base electrode at least during said arithmetic operation carried out by said arithmetic operation circuit,
• (e) a second impedance element connected between said second potential node and said output node, for forming a current path between said second potential node and said output node at least during said arithmetic operation, and
• (f) an FET circuit for controlling the on/off state of said bipolar transistor by controlling a formation of a current path between said second potential node and said first potential node, said FET circuit including:
• a first FET having its gate electrode connected with an output of said first means,
• a second FET having its gate electrode connected with an output of said second means, and
• a third FET having its gate electrode connected with a carry-in input,
• source-drain paths of said first, second and third FETs being connected between said first potential node and said base electrode of said bipolar transistor.