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US 4,789,957 AGranted
Status output for a bit slice ALU
AssigneeTexas Instruments Incorporated
InventorsJeffrey A. Niehaus, Jesse O. Englade
Life of this patent
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Abstract
A bit slice processor system includes a bit slice ALU that is cascadable to provide multiple length words. Each of the ALUs provides both command outputs and status outputs. The status outputs are interfaced with each of the package as are the command outputs. Each of the ALUs in the cascaded ALU are controlled by an instruction word to perform a predetermined processing function. Internal status information is processed to generate a command output and a status output. This command is transmitted simultaneously with the status to the remaining packages in the cascaded array to provide processing control.
Claims12
An expandable bit slice processor comprising:
- plurality of bit slice arithmetic logic units for processing data in accordance with one of a plurality of predetermined processing functions, each of said arithmetic logic units being n-bits in length;
- means for cascading said bit slice arithmetic logic units to provide an expanded arithmetic logic unit nXm bits in length to provide processing for an expanded length word where m is the number of said cascaded bit slice arithmetic logic units;
- first interface means for interfacing status information between said cascaded bit slice arithmetic logic units;
- and
- second interface means for interfacing control information between said cascaded bit slice arithmetic logic units;
- said first and second interface means operable to simultaneously interface control and status information, respectively;
- each of said bit slice arithmetic logic units having:
- status means for determining status information for the processed data in accordance with one of the predetermined processing functions by which the data is being processed and generating a status signal containing the status information;
- third interface means for interfacing said status information with said first interface means to transmit the predetermined status to all of said cascaded bit slice arithmetic logic units;
- control means for determining control information for the processed data and generating a control signal containing the control information, said control information determined in accordance with a predetermined control logic function that is a function of one of the predetermined processing functions by which the data is processed;
- and
- fourth interface means for interfacing the control signal with said second interface means such that the control signal is transmitted to all of the cascaded bit slice arithmetic units simultaneously with said status signal.
9 more elements
An expandable bit slice processor, comprising:
- a plurality of bit slice arithmetic logic units for processing data in accordance with one of a plurality of predetermined processing functions, each of said arithmetic logic units being n-bits in length;
- means for cascading said bit slice arithmetic logic units to provide an expanded word length nXm bits in length where m is the number of said cascaded bits slice arithmetic logic units;
- a control bus interfaced with each of said arithmetic logic units;
- a status bus interfaced with each of said arithmetic logic units;
- each of said arithmetic logic units having:
- first means for receiving an instruction word and selecting one of said predetermined processing functions;
- second means for receiving data and coupled to said first means for processing data in accordance with said selected predetermining processing functions;
- and
- status means for interfacing with the process data and generating status information in accordance with the selected processing function and generating a status signal for output to said status bus for interfacing with the remaining ones of said arithmetic logic units;
- and
- control means for interfacing with internal processed data for processing with a predetermined control logic function that is a function of said received instruction word and generating a control signal in response thereto for output to said control bus, said control signal interfaced through said control bus with the remaining ones of said arithmetic logic units.
8 more elements
Dependencies are inferred from the claim text.