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US 4,789,955 AGranted
Operation unit with an error amount calculating circuit for output data thereof
AssigneeHitachi, Ltd.
InventorYukio Umetani
Life of this patent
Estimating the term…
Abstract
An operation unit includes a first unit for calculating input data and for outputting an error data indicating an error generated as a result of the calculation by using such a mantissa data at a lower order as has been obtained midway of the calculation but is not used as an output result data; and a second unit for outputting error data of the calculation result data from the first-named error data and error data input accompanying the input data.
Claims7
An operation unit comprising:
- first means for executing a first calculation for operand data of floating point indication inputted to generate arithmetic result data having a mantissa part of first bit length and arithmetic error data having a mantissa part of second bit length and indicating an error generated by said calculation;
- and
- second means connected with said first means for performing a second calculation on both said arithmetic error data and an input error data indicating an error accompanying said input operand data to calculate final error data accompanying said arithmetic result data.
Dependencies are inferred from the claim text.