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US 4,789,951 AGranted
Programmable array logic cell
AssigneeAdvanced Micro Devices, Inc.
InventorsJohn M. Birkner, Danesh M. Tavana, Andrew K. Chan, Sing Y. Wong
Life of this patent
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Abstract
A programmable array logic cell 60 including a sum-of-products array having a single OR gate 70 for providing a sum signal, and including an XOR gate 80 for combining the sum signal with a product signal provided by an AND gate 78 from selected array input and/or feedback signals. The product signal can be the previous state output signal Q for a JK flip flop configuration, or a forced high or low signal for other configurations for programmable output signal polarity.
Claims5
A programmable logic cell comprising:
- a plurality of logical AND gates, each gate having a plurality of input terminals and an output line;
- a plurality of cell input lines, selectively connectable to the input terminals of selected AND gates;
- a single logic OR gate having input terminals connected to selected AND gate output lines, and having an output line;
- a logical XOR gate having a first input terminal connected to the OR gate output line, having a second input terminal connected to an AND gate output line, and having an XOR output line on which the XOR gate provides a state signal;
- memory means to store the XOR output state signal;
- a cell output line coupled to the OR gate output line for providing a cell output signal;
- and
- feedback means selectively connectable to apply the state signal to selected AND gate input terminals.
5 more elements
Dependencies are inferred from the claim text.