MOS I/O protection using switched body circuit design

A MOS integrated circuit including switched body circuitry that protects a system data line connected to an input pull up or pull down device, the circuit comprising:

• (a) a semiconductor substrate of a first conductivity type;
• (b) a well region of a second conductivity type opposite to that of the first conductivity type formed in a surface of the substrate;
• (c) first, second, third and fourth spaced-apart shallow diffusion regions of the first conductivity type formed in a surface of the well region, the first and fourth of these regions being electrically connected to the well region through ohmic contacts;
• (d) a first gate electrode overlying a first channel region between the second diffusion region and the third diffusion region, the first gate electrode and the second and third diffusion regions combining to define an MOS pull up or pull down transistor, the first gate electrode being connected to a V.sub.SS for a MOS pull up or to a V.sub.DD for a pull down;
• (e) an input pad connected to the second diffusion region and to a second gate electrode overlying a second channel region between the third diffusion region and the fourth diffusion region, the second gate electrode and the third and fourth diffusion regions combining to define a first switched body MOS transistor;
• and
• (f) a power supply pad connected to the third diffusion region and to a third gate electrode overlying a third channel region between the first diffusion region and the second diffusion region, the third gate electrode and the first and second diffusion regions combining to define a second switched body MOS transistor.

A MOS integrated circuit including switched body circuitry that protects a system data line connected to an output driver, the circuit comprising:

• (a) a semiconductor substrate of a first conductivity type;
• (b) a well region of a second conductivity type opposite to that of the first conductivity type formed in a surface of the substrate;
• (c) first, second, third and fourth spaced-apart shallow diffusion regions of the first conductivity type formed in a surface of the well region, the first and fourth of these regions being electrically connected to the well region through ohmic contacts;
• (d) a first gate electrode overlying a first channel region between the second diffusion region and the third diffusion region, the first gate electrode and the second and third diffusion regions combining to define an MOS output driver transistor, the first gate electrode being connected to receive a logic output signal;
• (e) an output pad connected to the second diffusion region and to a second gate electrode overlying a second channel region between the third diffusion region and the fourth diffusion region, the second gate electrode and the third and fourth diffusion regions combining to define a first switched body MOS transistor;
• and
• (f) a power supply pad connected to the third diffusion region and to a third gate electrode overlying a third channel region between the first diffusion region and the second diffusion region, the third gate electrode and the first and second diffusion regions combining to define a second switched body MOS transistor.