Control of signal timing apparatus in automatic test systems using minimal memory

Apparatus for supplying a signal after a predetermined time delay comprising:

• a base delay storage means for storing at least one first sequence of bits extending from a most significant bit to include a lesser significant bit, the at least one first sequence of bits being a digital representation of the value of higher order bits of a time delay;
• a first vernier delay storage means for storing at least one second sequence of bits extending from a first bit of equal significance to the lesser significant bit to a first least significant bit, the at least one second sequence of bits being a digital representation of the value of lower order bits of the time delay;
• first generating means coupled to the base delay storage means and to the first vernier delay storage means for receiving the digital representation of the value of the time delay therefrom, and also connected to receive a start signal, the first generating means for supplying a first signal an amount of time after receiving the start signal as represented by the first bit and the first sequence of bits;
• and
• first delay means connected to receive the first signal from the first generating means and connected to the first vernier delay storage means, the first delay means for supplying a first delayed signal an amount of time after receiving the first signal as represented by all of the second sequence of bits except the first bit.