Test device for a combinatorial logic circuit and integrated circuit including such a device
AssigneeU.S. Philips Corporation
InventorsDaniel Baschiera, Bernard Courtois
Life of this patent
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Abstract
This device and method for testing a combinative logic circuit (4), includes on the one hand a circuit generating test sequences (30) for applying test logic signals to N inputs of the combinative logic circuit and, on the other hand, an output circuit (5) to analyze the output signals of the combinative logic circuit. These test sequences are successively applied to each of the N inputs (E1, E2, E3 and E4) so that an alternating series, at least twice, of logic "1"'s and of logic "0"'s while a word of N-1 bits is applied to the other inputs to ensure the transmission of the said alternating series to the output of the combinative logic circuit.
Claims11
A device for generating N-bit test sequences for testing a combinatorial logic circuit having N inputs, where N is an integer greater than one, the device comprising:
- a. a feedback shift register operating as a pseudo-random sequence generator, and having output means at which an N-bit vector is supplied;
- b. means for selectively generating a one bit selection signal and and an (N-1)-bit non-selection signal from the N-bit vector, so that inversions in the selection signal appear at an output of the combinatorial logic circuit;
- c. means for inverting the selection signal at least twice in succession;
- and
- d. means for feeding said selection signal and said non-selection signal in parallel to respective ones of said N inputs.
An integrated circuit comprising:
- a. a user device for performing user functions comprising combinatorial logic and having N inputs;
- and
- b. means for generating N-bit test sequences to the N inputs comprising:
- i. a feedback shift register operating as a pseudo-random sequence generator, and having output means at which an N-bit vector is supplied;
- ii. means for selectively generating a one bit selection signal and an (N-1)-bit non-selection signal from the N-bit vector, so that inversions in the selection signal appear at an output of the combinatorial logic circuit;
- iii. means for inverting the selection signal at least twice in succession;
- and
- iv. output means for supplying said selection signal and said non-selection signal as said N-bit test sequence.
A method for testing a combinatorial logic circuit having N inputs, comprising the steps of:
- a. first generating a pseudo-random bit sequence in the form of an N-bit vector;
- b. second selectively generating selection and non-selection signals from said N-bit vector, said selection signal comprising one bit and said non-selection signal comprising (N-1) bits, said second generating being such that inversions in the selection signal appear at an output of the combinatorial logic circuit;
- c. inverting the selection signal at least twice in succession;
- d. supplying said twice inverted selection signal and said non-selection signals to respective ones of said N inputs, in parallel;
- and
- e. analyzing inversions in the selection signal at the output of the combinatorial logic to determine if there is a malfunction in the combinatorial logic.
Dependencies are inferred from the claim text.