ECL to GaaS logic conversion circuit with positive feedback

A gallium arsenide device for converting an ECL voltage signal to a gallium arsenide voltage signal, comprising:

• means for transforming the ECL voltage signal and a predetermined reference voltage into a corresponding signal and a reference current to provide pull up including a pair of gallium arsenide depletion mode field effect transistors;
• means for outputting the gallium arsenide voltage signal representation of the ECL voltage signal including a pair of gallium arsenide enhancement mode field effect transistors connected to said pair of gallium arsenide depletion mode field effect transistors;
• positive feedback means for increasing the gain of said pair of gallium arsenide enhancement mode field effect transistors and connected to said pair of gallium arsenide enhancement mode field effect transistor means;
• at least a third gallium arsenide depletion mode field effect transistor connected to a third gallium arsenide enhancement mode field effect transistor, said third gallium arsenide enhancement mode field effect transistor having a gate connected to an output of said pair of gallium arsenide depletion mode field effect transistors;
• wherein said third gallium arsenide depletion mode field effect transistor and said third gallium arsenide enhancement mode field effect transistor have a substantially similar structure and topology to said pair of gallium arsenide depletion mode and gallium arsenide enhancement mode transistors.

A gallium arsenide device for converting an ECL signal to a gallium arsenide signal, comprising:

• a first gallium arsenide depletion mode field effect transistor and a second gallium arsenide depletion mode field effect transistor, each having a respective gate, source and drain and having their drains connected to a first predetermined voltage source, said first gallium arsenide depletion mode field effect transistor having its gate coupled for receiving the ECL signal and said second gallium arsenide depletion mode field effect transistor having its gate connected to receive a predetermined reference voltage;
• a first gallium arsenide enhancement mode field effect transistor and a second gallium arsenide enhancement mode field effect transistor, each having a respective gate, source and drain and having their sources connected to a second predetermined voltage source, said first gallium arsenide enhancement mode field effect transistor having its drain connected to said source of said first gallium arsenide depletion mode field effect transistor, said second gallium arsenide enhancement mode field effect transistor having its gate connected to said source of said first gallium arsenide depletion mode field effect transistor and said second gallium arsenide enhancement mode field effect transistor having its drain connected to said source of said second gallium arsenide depletion mode field effect transistor and to said gate of said first gallium arsenide enhancement mode field effect transistor, the gallium arsenide signal appearing on said drain of said first gallium arsenide enhancement mode field effect transistor;
• a third gallium arsenide depletion mode field effect transistor having a gate, a source and a drain, having its gate connected to its source, is drain connected to said first predetermined voltage source and having a structure similar to said first gallium arsenide depletion mode field effect transistor and said second gallium arsenide depletion mode field effect transistor;
• and
• a third gallium arsenide enhancement mode field effect transistor having a gate, a source and a drain and having its drain connected to said source of said third gallium arsenide depletion mode field effect transistor, haing its source connected to said second predetermined voltage source and having its gate connected to said drain of said first gallium arsenide enhancement mode field effect transistor and having a structure similar to said first gallium arsenide depletion mode field effect transistor and said second gallium arsenide depletion mode field effect transistor;
• wherein said third depletion and enhancement transistors have a substantially similar structure to said first and second of depletion and enhancement transistors.