Temperature-compensated interface circuit between "OR-tied" connection of a PLA device and a TTL output buffer

A programmable logic array device having an "OR-tied" connection and used for driving an output buffer so as to provide a high speed of operation over a wide range of temperature variations, said device comprising:

• a plurality of input buffers (14a . . . 14n), each of said plurality of input buffers having an input for receiving an input logic signal and an output;
• a plurality of output transistors (Q1a . . . Q1n), each of said plurality of transistors having its base coupled to the respective outputs of said input buffers (14a . . . 14n), its collector connected to a supply potential, and its emitter connected to a common node defining the "OR-tied" connection (P);
• first generator means (40) for generating a first reference voltage (VB1) having a positive temperature coefficient;
• high level clamp means (30) responsive to the first reference voltage (VB1) for producing a first current (I.sub.1) which decreases with rising temperatures;
• second generator means for generating a second reference voltage (VB2) having a negative temperature coefficient;
• sensing means (26) having an input connected to the common node (P) to receive a voltage corresponding to the first current (I.sub.1) and being responsive to the second reference voltage (VB2) for producing a second current (I.sub.2) which increases with rising temperatures, said sensing means (26) combining said first and second currents (I.sub.1, I.sub.2) to generate a resultant base drive current (I.sub.x) which is higher at low temperatures and is smaller at higher temperatures;
• and
• the output buffer (36) having a phase splitter transistor (Q2) whose base is connected to receive the resultant base drive current (I.sub.x), whereby the switching speed of the phase splitter transistor (Q2) remains substantially constant over a wide range of temperature variations.