Integrated FET circuit to reduce switching noise

An integrated circuit structure comprising:

• a substrate having semiconductor areas forming a plurality of sub-transistors, each of said sub-transistors having a discrete gate, and
• resistance means comprising a doped region near the surface of said substrate, said resistance means serving to couple the gates of at least one pair of said sub-transistors in a series circuit so that a gate signal applied to a gate of a first sub-transistor of said series circuit propagates to the gates of consecutive sub-transistors in said circuit in a predetermined time interval, the propagation of said gate signal along said series circuit causing sequential conduction of ones of said sub-transistors.

An integrated circuit structure comprising:

• a substrate having semiconductor areas forming a first plurality of sub-transistors, each of said sub-transistors having a discrete gate,
• a plurality of coupling transistors, each coupling transistor having a source to drain current path, said source to drain current path being connected between the gates of two of said first plurality of sub-transistors so that a turn-on gate signal applied to the first gate of said first plurality of sub-transistors is propagated over a period of time by said coupling transistors to the gates of others of said first plurality of sub-transistors, ones of said first plurality of sub-transistors turning on at different times to prevent the large rate of change in power supply current that would be required if all the transistors of said first plurality turned on at the same time.