Decision timing control circuit
AssigneeFujitsu Limited
InventorsToshiaki Sakane, Noboru Iizuka, Takanori Iwamatsu
Life of this patent
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Abstract
A circuit is provided for controlling the decision timing of an A/D converter so that error rate becomes small. Error rate information is obtained based on the converted digital signal from the A/D converter. This information is used for controlling the phase of an A/D converter clock signal to thereby control the decision timing of the A/D converter.
Claims6
A decision timing control circuit having an actual and pseudo bit error rate, operatively connectable to receive a multi-level modulated signal having a clock signal with a phase, said decision timing control circuit comprising:
- demodulation means for demodulating the multi-level modulated signal and for outputting a corresponding demodulated multi-level signal;
- A/D conversion means, operatively connected to said demodulation means, for converting said demodulated multi-level signal into a corresponding digital output signal;
- clock recovery means, operatively connected to said demodulation means, for recovering the clock signal from said demodulated multi-level signal and for providing a recovered clock signal output;
- variable phase shifting means, operatively connected to said clock recovery means and said A/D conversion means, for phase shifting and providing said recovered clock signal to said A/D conversion means by phase shifting said recovered clock signal in accordance with a control signal;
- error rate detection means, operatively connected to said A/D conversion means, for receiving said digital output signal and for generating an error rate information signal corresponding to the pseudo error rate of said digital output signal;
- and
- phase control means, operatively connected to said error rate detection means and said variable phase shifting means, for generating and providing the control signal to said variable phase shifting means to vary an amount of phase shift of said variable phase shifting means, responsive to said error rate information signal so that the actual error rate becomes small on the basis of said error rate information signal.
A decision timing control circuit having an actual and pseudo error rate operatively connectable to receive a multi-level signal having a clock signal with a phase, said decision timing control circuit comprising:
- A/D conversion means, operatively connectable to receive the multi-level signal, for converting the multi-level signal into a corresponding digital output signal;
- clock recovery means, operatively connectable to receive the multi-level signal, for recovering the clock signal from the multi-level signal and for providing a recovered clock signal output;
- variable phase shifting means, operatively connected to said clock recovery means and said A/D conversion means, for phase shifting and providing said recovered clock signal to said A/D conversion means by phase shifting said recovered clock signal in accordance with a control signal;
- error rate detection means, operatively connected to said A/D conversion means, for receiving said digital output signal and for generating an error rate information signal corresponding to the pseudo error rate of said digital output signal;
- and
- phase control means, operatively connected to said error rate detection means and said variable phase shifting means, for generating and providing the control signal to said variable phase shifting means to vary an amount of phase shift of said variable phase shifting means, responsive to said error rate information signal so that the actual error rate becomes small on the basis of said error rate information signal.
Dependencies are inferred from the claim text.