US 4,788,695 A · System for decoding self-clocking data signals

Abstract

A coherent detection and decoding circuit coherently recovers data embedded in a self-clocking data signal by recovering the clock in one integrate and dump circuit and recovering the data in a second integrate and dump circuit. The two integrate and dump circuits are connected to the source of self-clocking data signal and to one of the outputs from a clock phase select switch which produces an inphase clock signal and a NOT inphase clock signal. The inphase clock signal is connected to the integrate and dump circuit which produces the output data signal and the NOT inphase clock signal is connected to the clock recovery integrate and dump circuit. When the presence of a data pulse is detected in the clock phase detection circuit the output signal is coupled to the clock phase select switch so as to reverse the output clock signals and synchronize the inphase clock signal with the data embedded in the self-clocking data input signal.

Claims15

Dependent claims

A coherent detection and decoding system for decoding self-clocking data signals comprising,

a source of random self-clocking data signals,
a clock phase select switch for generating an inphase and a not inphase clock signal whose phase is unknown,
a data channel having first integrate and dump circuit means coupled to said inphase clock signal and said random self-clocking data signals for producing a decoded data output signal,
a phase select channel having second integrate and dump circuit means coupled to said not inphase clock signal and to said self-clocking data signals for producing a decoded data output signal when the data is inphase with the not inphase clock signal and is out of phase with the inphase clock signal, and
said data output signal from said second integrate and dump circuit means being coupled to a second input to said clock phase select switch for setting the correct inphase output and NOT inphase output from said clock phase select switch.

2 more elements

A coherent detection and decoding system for decoding self-clocking data signals comprising:

a source of self-clocking data signals to be decoded,
a source of recovered clock signals whose phase in unknown,
a clock phase select channel comprising a first integrate and dump circuit coupled at its input to said self-clocking data signals and to said recovered clock signals whose phase is unknown,
a phase select logic circuit coupled to the output of said first ingegrate and dump circuit for detecting the presence of a data signal which occurs during the integration period of said first integrate and dump circuit which indicates an out of phase data condition,
logic switch means coupled at its input to the output of said phase select logic circuit and to said source of recovered clock signals for generating clock signals that are inphase and NOT inphase with said data signals,
said logic switch means being adapted to be switched when activated by an output signal from said phase select logic circuit, so that
said NOT inphase recovered clock signal from said logic switch means being connected to the input of said clock phase select channel, and
a data channel comprising a second integrate and dump circuit coupled to said inphase clock signals from said logic switch and to said source of self-clocking data signals for generating decoded data output signals.

5 more elements

Dependencies are inferred from the claim text.

System for decoding self-clocking data signals

Life of this patent

System for decoding self-clocking data signals

Life of this patent

Abstract

Claims15