Memory test apparatus

Abstract

A memory test apparatus for testing a high-performance memory having two or more memory functions, including a pattern generator for generating an algorithmic pattern to be inputted to a first memory block of a memory under test having at least two memory blocks, an auxiliary pattern generator for storing an output from the algorithmic pattern generator and for outputting an expected value to a second memory block of the memory under test at a preset timing based on the stored output, a comparator for comparing outputs from the first and second memory blocks with expected values for the memory blocks, and a memory for storing an output from the comparator. Since the algorithmic pattern generator and the auxiliary pattern generator are included, the test apparatus has such an affect that even if the first and second memory blocks of the memory under test operate asynchronously, the data transfer function therebetween and the performance related to the operation timing can be tested, thus providing a highly precise memory test apparatus.

Dependencies are inferred from the claim text.